reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/X86/X86GenRegisterInfo.inc

 4337   extern const TargetRegisterClass GR16RegClass;

References

gen/lib/Target/X86/X86GenFastISel.inc

  465     return fastEmitInst_r(X86::JMP16r, &X86::GR16RegClass, Op0, Op0IsKill);
  525     return fastEmitInst_r(X86::LZCNT16rr, &X86::GR16RegClass, Op0, Op0IsKill);
  623     return fastEmitInst_r(X86::POPCNT16rr, &X86::GR16RegClass, Op0, Op0IsKill);
  781     return fastEmitInst_r(X86::TZCNT16rr, &X86::GR16RegClass, Op0, Op0IsKill);
  818   return fastEmitInst_r(X86::BSF16rr, &X86::GR16RegClass, Op0, Op0IsKill);
 2518     return fastEmitInst_r(X86::CALL16r, &X86::GR16RegClass, Op0, Op0IsKill);
 4498     return fastEmitInst_r(X86::JMP16r_NT, &X86::GR16RegClass, Op0, Op0IsKill);
 4536     return fastEmitInst_r(X86::CALL16r_NT, &X86::GR16RegClass, Op0, Op0IsKill);
 5998   return fastEmitInst_rr(X86::ADD16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 6190   return fastEmitInst_rr(X86::AND16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 6959   return fastEmitInst_rr(X86::IMUL16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 7197   return fastEmitInst_rr(X86::OR16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 8149   return fastEmitInst_rr(X86::SUB16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 8823   return fastEmitInst_rr(X86::XOR16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 9405   return fastEmitInst_rr(X86::BT16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 9468   return fastEmitInst_rr(X86::CMP16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
13629   return fastEmitInst_ri(X86::ADD16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
13658   return fastEmitInst_ri(X86::AND16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
13721   return fastEmitInst_ri(X86::IMUL16rri, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
13749   return fastEmitInst_ri(X86::OR16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
13840   return fastEmitInst_ri(X86::SHL16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
13876   return fastEmitInst_ri(X86::SAR16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
13912   return fastEmitInst_ri(X86::SHR16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
13948   return fastEmitInst_ri(X86::SUB16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
13977   return fastEmitInst_ri(X86::XOR16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
14018   return fastEmitInst_ri(X86::BT16ri8, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
14258   return fastEmitInst_ri(X86::ADD16ri8, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
14273   return fastEmitInst_ri(X86::AND16ri8, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
14288   return fastEmitInst_ri(X86::IMUL16rri8, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
14303   return fastEmitInst_ri(X86::OR16ri8, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
14318   return fastEmitInst_ri(X86::SUB16ri8, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
14333   return fastEmitInst_ri(X86::XOR16ri8, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
14576   return fastEmitInst_i(X86::MOV16ri, &X86::GR16RegClass, imm0);

gen/lib/Target/X86/X86GenRegisterInfo.inc

 5207   &X86::GR16RegClass,
 5317   &X86::GR16RegClass,
 7709     &X86::GR16RegClass,

lib/Target/X86/X86AsmPrinter.cpp

  395       !X86::GR16RegClass.contains(Reg) &&

lib/Target/X86/X86DomainReassignment.cpp

   47          X86::GR16RegClass.hasSubClassEq(RC) ||
   71   if (X86::GR16RegClass.hasSubClassEq(SrcRC))
  225          X86::GR16RegClass.contains(DstReg)))
  230          X86::GR16RegClass.contains(SrcReg)))

lib/Target/X86/X86FastISel.cpp

 1793     RC = &X86::GR16RegClass;
 1886     { &X86::GR16RegClass, X86::AX,  X86::DX, {
 1988     unsigned SourceSuperReg = createResultReg(&X86::GR16RegClass);
 1989     unsigned ResultSuperReg = createResultReg(&X86::GR16RegClass);

lib/Target/X86/X86ISelLowering.cpp

  179   addRegisterClass(MVT::i16, &X86::GR16RegClass);
 3237           RC = &X86::GR16RegClass;
31275         MF->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
45759          RC.hasSuperClassEq(&X86::GR16RegClass) ||
45829           return std::make_pair(0U, &X86::GR16RegClass);
45853         return std::make_pair(0U, &X86::GR16RegClass);
46048         : Size == 16 ? (is64Bit ? &X86::GR16RegClass : &X86::GR16_NOREXRegClass)

lib/Target/X86/X86InstrInfo.cpp

 2850   if (X86::GR16RegClass.hasSubClassEq(RC) ||
 2976   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
 3083     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");

lib/Target/X86/X86InstructionSelector.cpp

  173       return &X86::GR16RegClass;
  206   } else if (RC == &X86::GR16RegClass) {
  221   if (X86::GR16RegClass.contains(Reg))
  222     return &X86::GR16RegClass;
  747   } else if (DstRC == &X86::GR16RegClass) {
 1690     Register SourceSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
 1691     Register ResultSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);

lib/Target/X86/X86RegisterBankInfo.cpp

   47       X86::GR16RegClass.hasSubClassEq(&RC) ||

lib/Target/X86/X86SpeculativeLoadHardening.cpp

 2261       &X86::GR8RegClass, &X86::GR16RegClass, &X86::GR32RegClass,

tools/llvm-exegesis/lib/X86/Target.cpp

  668   if (X86::GR16RegClass.contains(Reg))