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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenAsmMatcher.inc 4967 Inst.addOperand(MCOperand::createReg(X86::AX));
7135 case X86::AX: OpKind = MCK_AX; break;
gen/lib/Target/X86/X86GenCallingConv.inc 2690 X86::AX, X86::DX, X86::CX
2959 X86::AX, X86::DX, X86::CX
3061 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI
3458 X86::AX, X86::DX, X86::CX, X86::R8W
3631 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W
3831 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
gen/lib/Target/X86/X86GenInstrInfo.inc16571 static const MCPhysReg ImplicitList9[] = { X86::AX, X86::EFLAGS, 0 };
16572 static const MCPhysReg ImplicitList10[] = { X86::AX, 0 };
16596 static const MCPhysReg ImplicitList34[] = { X86::AX, X86::DX, 0 };
16597 static const MCPhysReg ImplicitList35[] = { X86::AX, X86::DX, X86::EFLAGS, 0 };
16602 static const MCPhysReg ImplicitList40[] = { X86::AL, X86::EFLAGS, X86::AX, 0 };
16617 static const MCPhysReg ImplicitList55[] = { X86::AX, X86::ESI, 0 };
16627 static const MCPhysReg ImplicitList65[] = { X86::DX, X86::AX, 0 };
16650 static const MCPhysReg ImplicitList88[] = { X86::AX, X86::ECX, X86::EDI, 0 };
16651 static const MCPhysReg ImplicitList89[] = { X86::AX, X86::RCX, X86::RDI, 0 };
16657 static const MCPhysReg ImplicitList95[] = { X86::AX, X86::EDI, X86::DF, 0 };
gen/lib/Target/X86/X86GenRegisterInfo.inc 1373 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W,
1383 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP,
1503 X86::AX, X86::CX, X86::DX, X86::BX,
gen/lib/Target/X86/X86GenSubtargetInfo.inc20829 && MI->getOperand(1).getReg() != X86::AX
22435 && MI->getOperand(1).getReg() != X86::AX
lib/Target/X86/Disassembler/X86Disassembler.cpp 270 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
507 ALL_REGS
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 97 {codeview::RegisterId::AX, X86::AX},
618 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
630 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
667 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
668 return X86::AX;
703 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
739 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
lib/Target/X86/X86FastISel.cpp 1879 { &X86::GR8RegClass, X86::AX, 0, {
1886 { &X86::GR16RegClass, X86::AX, X86::DX, {
1887 { X86::IDIV16r, X86::CWD, Copy, X86::AX, S }, // SDiv
1889 { X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U }, // UDiv
1991 TII.get(Copy), SourceSuperReg).addReg(X86::AX);
2947 static const MCPhysReg Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX };
lib/Target/X86/X86FixupBWInsts.cpp 345 MI->getOperand(0).getReg() == X86::AX &&
lib/Target/X86/X86FrameLowering.cpp 200 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
lib/Target/X86/X86ISelDAGToDAG.cpp 4639 LoReg = X86::AX;
4828 LoReg = X86::AX; HiReg = X86::DX;
4867 Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, SDValue(Move, 0),
lib/Target/X86/X86ISelLowering.cpp26698 case MVT::i16: Reg = X86::AX; size = 2; break;
lib/Target/X86/X86InstructionSelector.cpp 1568 X86::AX,
1577 X86::AX,
1580 {X86::IDIV16r, X86::CWD, Copy, X86::AX, S}, // SDiv
1582 {X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U}, // UDiv
1693 .addReg(X86::AX);
lib/Target/X86/X86MCInstLower.cpp 303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
322 if (Op0 == X86::AX && Op1 == X86::AL)
326 if (Op0 == X86::EAX && Op1 == X86::AX)
364 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
1069 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI);
1069 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI);
lib/Target/X86/X86SelectionDAGInfo.cpp 117 ValReg = X86::AX;
unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp 35 X86::AL, X86::AH, X86::AX, X86::EAX, X86::HAX, X86::RAX};
65 ASSERT_THAT(&Cache.getRegister(X86::AX), &Cache.getRegister(X86::AX));
65 ASSERT_THAT(&Cache.getRegister(X86::AX), &Cache.getRegister(X86::AX));
unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp 78 EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::AX);
80 EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[0], X86::AX);
393 IT.getValueFor(IT.Instr.Variables[0]) = MCOperand::createReg(X86::AX);
397 EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::AX, APInt())));