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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenAsmMatcher.inc 7086 case X86::AL: OpKind = MCK_AL; break;
gen/lib/Target/X86/X86GenCallingConv.inc 2680 X86::AL, X86::DL, X86::CL
2949 X86::AL, X86::DL, X86::CL
3051 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL
3448 X86::AL, X86::DL, X86::CL, X86::R8B
3621 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B
3821 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
gen/lib/Target/X86/X86GenDAGISel.inc32320 /* 67080*/ OPC_EmitCopyToReg, 0, X86::AL,
32484 /* 67424*/ OPC_EmitCopyToReg, 0, X86::AL,
gen/lib/Target/X86/X86GenFastISel.inc 6952 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::AL).addReg(Op0);
gen/lib/Target/X86/X86GenInstrInfo.inc16570 static const MCPhysReg ImplicitList8[] = { X86::AL, X86::EFLAGS, 0 };
16573 static const MCPhysReg ImplicitList11[] = { X86::AL, 0 };
16598 static const MCPhysReg ImplicitList36[] = { X86::AL, X86::AH, X86::EFLAGS, 0 };
16602 static const MCPhysReg ImplicitList40[] = { X86::AL, X86::EFLAGS, X86::AX, 0 };
16614 static const MCPhysReg ImplicitList52[] = { X86::AL, X86::ESI, 0 };
16629 static const MCPhysReg ImplicitList67[] = { X86::DX, X86::AL, 0 };
16644 static const MCPhysReg ImplicitList82[] = { X86::AL, X86::ECX, X86::EDI, 0 };
16646 static const MCPhysReg ImplicitList84[] = { X86::AL, X86::RCX, X86::RDI, 0 };
16653 static const MCPhysReg ImplicitList91[] = { X86::AL, X86::EDI, X86::DF, 0 };
16669 static const MCPhysReg ImplicitList107[] = { X86::AL, X86::EBX, 0 };
gen/lib/Target/X86/X86GenRegisterInfo.inc 1146 { X86::AL },
1313 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B,
1333 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH,
1353 X86::AL, X86::CL, X86::DL, X86::BL,
6255 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B };
6271 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL };
lib/Target/X86/Disassembler/X86Disassembler.cpp 270 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
507 ALL_REGS
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 89 {codeview::RegisterId::AL, X86::AL},
618 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
630 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
631 return X86::AL;
667 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
703 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
739 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
lib/Target/X86/X86CallLowering.cpp 439 .addDef(X86::AL)
441 MIB.addUse(X86::AL, RegState::Implicit);
lib/Target/X86/X86FastISel.cpp 1880 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AL, S }, // SDiv
1882 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AL, U }, // UDiv
2947 static const MCPhysReg Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX };
2962 TII.get(TargetOpcode::COPY), X86::AL)
3468 X86::AL).addImm(NumXMMRegs);
3528 MIB.addReg(X86::AL, RegState::Implicit);
lib/Target/X86/X86FixupBWInsts.cpp 346 MI->getOperand(1).getReg() == X86::AL)
lib/Target/X86/X86FrameLowering.cpp 201 Reg == X86::AH || Reg == X86::AL)
lib/Target/X86/X86ISelDAGToDAG.cpp 4634 LoReg = X86::AL;
4824 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
lib/Target/X86/X86ISelLowering.cpp 3378 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3468 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
3469 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3470 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
3899 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
26697 case MVT::i8: Reg = X86::AL; size = 1; break;
lib/Target/X86/X86InstructionSelector.cpp 1571 {X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AL, S}, // SDiv
1573 {X86::DIV8r, 0, X86::MOVZX16rr8, X86::AL, U}, // UDiv
lib/Target/X86/X86MCInstLower.cpp 303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
322 if (Op0 == X86::AX && Op1 == X86::AL)
364 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
lib/Target/X86/X86SelectionDAGInfo.cpp 133 ValReg = X86::AL;
150 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Val, InFlag);
unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp 67 .addReg(X86::AL)
73 RegisterValue{X86::AL, APInt(8, "-1", 10)},
unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp 35 X86::AL, X86::AH, X86::AX, X86::EAX, X86::HAX, X86::RAX};
52 sum |= RegisterAliasingTracker(RegInfo, X86::AL).aliasedBits();
unittests/tools/llvm-exegesis/X86/TargetTest.cpp 155 const unsigned Reg = X86::AL;