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References

gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc
 2251   { 2049 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
 2252   { 2049 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
 2253   { 2049 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12 }, },
 2254   { 2049 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
 2255   { 2049 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_2__SImm121_0, AMFBS_None, { MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
 2256   { 2049 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
 2257   { 2054 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
 2258   { 2054 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12 }, },
 2259   { 2054 /* jr */, RISCV::JALR, Convert__regX0__Reg1_2__SImm121_0, AMFBS_None, { MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
 2319   { 2309 /* ret */, RISCV::JALR, Convert__regX0__regX1__imm_95_0, AMFBS_None, {  }, },
gen/lib/Target/RISCV/RISCVGenAsmWriter.inc
 2600   case RISCV::JALR:
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc
  572     case RISCV::JALR: {
 1363       OutInst.setOpcode(RISCV::JALR);
 1379       OutInst.setOpcode(RISCV::JALR);
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc
  763     case RISCV::JALR:
gen/lib/Target/RISCV/RISCVGenMCPseudoLowering.inc
   29       TmpInst.setOpcode(RISCV::JALR);
   44       TmpInst.setOpcode(RISCV::JALR);
   58       TmpInst.setOpcode(RISCV::JALR);
   71       TmpInst.setOpcode(RISCV::JALR);
lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  130     TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
  133     TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);