reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

 2311   extern const TargetRegisterClass HvxVRRegClass;

References

gen/lib/Target/Hexagon/HexagonGenDAGISel.inc

72556   int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);

gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

 2640   &Hexagon::HvxVRRegClass,
 2970     &Hexagon::HvxVRRegClass,

lib/Target/Hexagon/HexagonAsmPrinter.cpp

  271   unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;

lib/Target/Hexagon/HexagonBitSimplify.cpp

  916       return &Hexagon::HvxVRRegClass;

lib/Target/Hexagon/HexagonBitTracker.cpp

  119     for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass,
  148       return Hexagon::HvxVRRegClass;

lib/Target/Hexagon/HexagonCopyToCombine.cpp

  232   if (Hexagon::HvxVRRegClass.contains(Reg))
  592   } else if (Hexagon::HvxVRRegClass.contains(LoRegDef)) {

lib/Target/Hexagon/HexagonFrameLowering.cpp

 1664   auto *RC = &Hexagon::HvxVRRegClass;
 1700   auto *RC = &Hexagon::HvxVRRegClass;
 1754   unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
 1755   unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
 1801   unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
 1802   unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
 1841   unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
 1869   unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);

lib/Target/Hexagon/HexagonISelLowering.cpp

  439     unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
 3033         return {0u, &Hexagon::HvxVRRegClass};
 3036           return {0u, &Hexagon::HvxVRRegClass};
 3212       return std::make_pair(&Hexagon::HvxVRRegClass, 1);

lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

   25     addRegisterClass(MVT::v64i8,  &Hexagon::HvxVRRegClass);
   26     addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass);
   27     addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass);
   44     addRegisterClass(MVT::v128i8,  &Hexagon::HvxVRRegClass);
   45     addRegisterClass(MVT::v64i16,  &Hexagon::HvxVRRegClass);
   46     addRegisterClass(MVT::v32i32,  &Hexagon::HvxVRRegClass);

lib/Target/Hexagon/HexagonInstrInfo.cpp

  846   if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
  866       Hexagon::HvxVRRegClass.contains(DestReg)) {
  871       Hexagon::HvxVRRegClass.contains(SrcReg)) {
  920   } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
  980   } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
 1096       unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
 1118       unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
 2697     unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
 4214       return HRI.getSpillSize(Hexagon::HvxVRRegClass);

lib/Target/Hexagon/HexagonRegisterInfo.cpp

  247   bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID();
  248   bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID();