reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/ARM/ARMGenRegisterInfo.inc

 3616   extern const TargetRegisterClass tGPRRegClass;

References

gen/lib/Target/ARM/ARMGenFastISel.inc

  102     return fastEmitInst_r(ARM::tBX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
  105     return fastEmitInst_r(ARM::BMOVPCRX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
  108     return fastEmitInst_r(ARM::BX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
  603   return fastEmitInst_r(ARM::WIN__DBZCHK, &ARM::tGPRRegClass, Op0, Op0IsKill);
 1592     return fastEmitInst_r(ARM::tREV, &ARM::tGPRRegClass, Op0, Op0IsKill);
 2743     return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2805     return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2829     return fastEmitInst_rr(ARM::tInt_eh_sjlj_longjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2850     return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp_nofp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2853     return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2856     return fastEmitInst_rr(ARM::tInt_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3009     return fastEmitInst_rr(ARM::tSUBSrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3407     return fastEmitInst_rr(ARM::tADDrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3520     return fastEmitInst_rr(ARM::tAND, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4151     return fastEmitInst_rr(ARM::tMUL, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4268     return fastEmitInst_rr(ARM::tORR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4345     return fastEmitInst_rr(ARM::tROR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4438     return fastEmitInst_rr(ARM::tLSLrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4613     return fastEmitInst_rr(ARM::tASRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4634     return fastEmitInst_rr(ARM::tLSRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4706     return fastEmitInst_rr(ARM::tSUBrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 5070     return fastEmitInst_rr(ARM::tEOR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 6110     return fastEmitInst_ri(ARM::tLSLri, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
 6381     return fastEmitInst_ri(ARM::tSUBSi3, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
 6453     return fastEmitInst_ri(ARM::tADDi3, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
 6484     return fastEmitInst_ri(ARM::tADDi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
 6511     return fastEmitInst_ri(ARM::tCMPi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
 6529     return fastEmitInst_ri(ARM::tCMPi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
 6547     return fastEmitInst_ri(ARM::tSUBSi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);

gen/lib/Target/ARM/ARMGenRegisterInfo.inc

 5052   &ARM::tGPRRegClass,
 5066   &ARM::tGPRRegClass,
 5080   &ARM::tGPRRegClass,
 5122   &ARM::tGPRRegClass,
 5140   &ARM::tGPRRegClass,
 8028     &ARM::tGPRRegClass,

lib/Target/ARM/ARMFastISel.cpp

  849     const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
 1063       unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass
 1659     RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
 2494     const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
 2624     /* Thumb    */ { &ARM::tGPRRegClass,    &ARM::rGPRRegClass    }
 2697   bool setsCPSR = &ARM::tGPRRegClass == RC;

lib/Target/ARM/ARMISelLowering.cpp

  687     addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
 3842     RC = &ARM::tGPRRegClass;
 3914       AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
 4063           RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
 9359   const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass
 9473   const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass
 9852             !ARM::tGPRRegClass.contains(Reg) &&
 9855         if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
10053   TRC = IsThumb ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
10709     Register TmpReg = MRI.createVirtualRegister(isThumb1 ? &ARM::tGPRRegClass
15683         return RCPair(0U, &ARM::tGPRRegClass);
15691         return RCPair(0U, &ARM::tGPRRegClass);

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

  694       NewBase = findFreeReg(isThumb1 ? ARM::tGPRRegClass : ARM::GPRRegClass);

lib/Target/ARM/Thumb1FrameLowering.cpp

  464     return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) &&
  829     if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
  837     if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
  955     if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
  965     if ((ARM::tGPRRegClass.contains(Reg)) &&
 1030     if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))

lib/Target/ARM/Thumb1InstrInfo.cpp

   50       || !ARM::tGPRRegClass.contains(DestReg))
   82   assert((RC == &ARM::tGPRRegClass ||
   86   if (RC == &ARM::tGPRRegClass ||
  111       (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
  115   if (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||

lib/Target/ARM/ThumbRegisterInfo.cpp

   48   if (ARM::tGPRRegClass.hasSubClassEq(RC))
   49     return &ARM::tGPRRegClass;
   58   return &ARM::tGPRRegClass;
  146     LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
  536       VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);