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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenDAGISel.inc15026 /* 32270*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
15031 /* 32289*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
21175 /* 45501*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
21192 /* 45545*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
21209 /* 45589*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
37169 /* 81798*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
37176 /* 81825*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
37421 /* 82399*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
37428 /* 82426*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
39253 /* 86359*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41095 /* 90200*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41102 /* 90227*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41344 /* 90836*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41351 /* 90863*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41809 /* 91947*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41817 /* 91976*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41825 /* 92005*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41835 /* 92045*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41847 /* 92077*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41855 /* 92106*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41863 /* 92135*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41873 /* 92175*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41894 /* 92221*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41902 /* 92250*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41910 /* 92279*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41920 /* 92319*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41932 /* 92351*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41940 /* 92380*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41948 /* 92409*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41958 /* 92449*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
41992 /* 92531*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
42000 /* 92560*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
42010 /* 92599*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
43067 /* 94887*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
43075 /* 94916*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
43083 /* 94945*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
43093 /* 94985*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
43105 /* 95017*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
43113 /* 95046*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
43121 /* 95075*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
43131 /* 95115*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
43163 /* 95193*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
43171 /* 95222*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
43181 /* 95261*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
43921 /* 96970*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
43931 /* 97008*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
44077 /* 97347*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
44085 /* 97376*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
44095 /* 97415*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
44336 /* 97938*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
44350 /* 97980*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
44368 /* 98028*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
44382 /* 98070*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
44406 /* 98128*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
44420 /* 98170*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
44439 /* 98219*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
44453 /* 98261*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
44586 /* 98603*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
44596 /* 98641*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
45233 /*100110*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
45294 /*100262*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
45302 /*100291*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
45312 /*100330*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
45324 /*100362*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
45332 /*100391*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
45342 /*100430*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
45390 /*100550*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
45398 /*100579*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
45408 /*100618*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
45420 /*100650*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
45428 /*100679*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
45438 /*100718*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
46520 /*103165*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
46535 /*103207*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
46566 /*103291*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
46581 /*103333*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
53703 /*120218*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
53713 /*120242*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
53722 /*120263*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
53746 /*120315*/ OPC_EmitInteger, MVT::i32, ARM::ssub_0,
55149 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
55150 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), SDLoc(N),
55157 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
55158 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue()/2, SDLoc(N),
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 8440 { ARM::dsub_0, ARM::dsub_1, ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, 0, ARM::dsub_6, 0, 0, 0, 0, 0, ARM::qsub_0, ARM::qsub_1, 0, 0, ARM::ssub_0, ARM::ssub_1, ARM::ssub_2, ARM::ssub_3, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, 0, 0, ARM::ssub_12, ARM::ssub_13, 0, 0, ARM::ssub_0_ssub_1_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_2_ssub_3_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, 0, 0, 0, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, },
lib/Target/ARM/A15SDOptimizer.cpp 148 return ARM::ssub_0;
158 if (!MI) return ARM::ssub_0;
162 if (!MO) return ARM::ssub_0;
171 return ARM::ssub_0;
265 EC->getOperand(1).getSubReg() == ARM::ssub_0) {
547 case ARM::ssub_0: Lane = 0; break;
lib/Target/ARM/ARMAsmPrinter.cpp 285 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
lib/Target/ARM/ARMBaseInstrInfo.cpp 921 BeginIdx = ARM::ssub_0;
1596 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1598 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
4873 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4913 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
5184 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
5265 MOReg->getSubReg(), ARM::ssub_0));
5293 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
5318 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
lib/Target/ARM/ARMISelDAGToDAG.cpp 1704 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32);
1738 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32);