|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 7866 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::rGPRRegClassID>());
7880 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::rGPRRegClassID>());
7894 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::rGPRRegClassID>());
gen/lib/Target/ARM/ARMGenAsmWriter.inc12568 MRI.getRegClass(ARM::rGPRRegClassID).contains(MI->getOperand(0).getReg()) &&
12578 MRI.getRegClass(ARM::rGPRRegClassID).contains(MI->getOperand(0).getReg()) &&
12592 MRI.getRegClass(ARM::rGPRRegClassID).contains(MI->getOperand(0).getReg()) &&
12602 MRI.getRegClass(ARM::rGPRRegClassID).contains(MI->getOperand(0).getReg()) &&
12616 MRI.getRegClass(ARM::rGPRRegClassID).contains(MI->getOperand(0).getReg()) &&
gen/lib/Target/ARM/ARMGenDAGISel.inc 3340 /* 6738*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
3343 /* 6749*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
3358 /* 6795*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
3361 /* 6806*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
3376 /* 6852*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
3379 /* 6863*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10716 /* 22648*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10731 /* 22686*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10746 /* 22724*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10761 /* 22762*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10776 /* 22800*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10791 /* 22838*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10814 /* 22890*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10829 /* 22928*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10844 /* 22966*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10859 /* 23004*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10874 /* 23042*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10889 /* 23080*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10918 /* 23142*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10934 /* 23181*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10950 /* 23220*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10966 /* 23259*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10982 /* 23298*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
10998 /* 23337*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
11022 /* 23390*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
11038 /* 23429*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
11054 /* 23468*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
11070 /* 23507*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
11086 /* 23546*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
11102 /* 23585*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
13286 /* 28440*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
13289 /* 28451*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
13304 /* 28497*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
13307 /* 28508*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
13322 /* 28554*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
13325 /* 28565*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
31465 /* 69210*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
31468 /* 69221*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
31483 /* 69267*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
31486 /* 69278*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
31501 /* 69324*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
31504 /* 69335*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
36843 /* 81059*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
46205 /*102441*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
46505 /*103123*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
46551 /*103249*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
48658 /*108180*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
48672 /*108218*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
48686 /*108256*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
48700 /*108294*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
48714 /*108332*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
48728 /*108370*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
48855 /*108673*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
48869 /*108711*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
48883 /*108749*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
48897 /*108787*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
48911 /*108825*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
48925 /*108863*/ OPC_EmitInteger, MVT::i32, ARM::rGPRRegClassID,
gen/lib/Target/ARM/ARMGenGlobalISel.inc 943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
948 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
972 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1045 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1063 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1069 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1132 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1138 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1205 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1211 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1354 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1355 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1402 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1403 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1472 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1477 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1478 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1525 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1526 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
3538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3544 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
3659 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
3660 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4427 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4433 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4729 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4834 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4921 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4938 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5041 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5052 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5210 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5215 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5264 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5761 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5841 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5922 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5933 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6004 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6015 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6086 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6097 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6164 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6174 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6246 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6256 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6328 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6338 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6399 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6405 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6459 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6465 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6524 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6530 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6594 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6600 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6664 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6670 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6729 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6734 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6744 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6804 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6814 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6874 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6884 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
6933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
6962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7025 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
7044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7050 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
7456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
11729 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
11730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13769 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
14078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14084 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
14496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14503 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14561 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
14636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
14663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15792 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15793 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15833 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15834 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15855 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15856 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15897 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15938 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15939 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16002 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16212 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
16474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
16476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21250 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21674 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21897 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
21919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21921 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
21943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
21967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21969 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21970 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
21991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
21994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
22455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
23823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23889 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
24021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
24043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
24065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
24637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25054 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
25079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
25104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25171 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
25187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
25188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
25231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
25232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
25233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
29723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
29724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
29997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
29998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
30085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
30086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5394 static const MCOperandInfo OperandInfo82[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5396 static const MCOperandInfo OperandInfo84[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5401 static const MCOperandInfo OperandInfo89[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
5401 static const MCOperandInfo OperandInfo89[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
5402 static const MCOperandInfo OperandInfo90[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5403 static const MCOperandInfo OperandInfo91[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5403 static const MCOperandInfo OperandInfo91[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5404 static const MCOperandInfo OperandInfo92[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5404 static const MCOperandInfo OperandInfo92[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5405 static const MCOperandInfo OperandInfo93[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
5407 static const MCOperandInfo OperandInfo95[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
5408 static const MCOperandInfo OperandInfo96[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5410 static const MCOperandInfo OperandInfo98[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5410 static const MCOperandInfo OperandInfo98[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5410 static const MCOperandInfo OperandInfo98[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5411 static const MCOperandInfo OperandInfo99[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5411 static const MCOperandInfo OperandInfo99[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5412 static const MCOperandInfo OperandInfo100[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5412 static const MCOperandInfo OperandInfo100[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5413 static const MCOperandInfo OperandInfo101[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5413 static const MCOperandInfo OperandInfo101[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5413 static const MCOperandInfo OperandInfo101[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5414 static const MCOperandInfo OperandInfo102[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5414 static const MCOperandInfo OperandInfo102[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5415 static const MCOperandInfo OperandInfo103[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5416 static const MCOperandInfo OperandInfo104[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
5416 static const MCOperandInfo OperandInfo104[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
5417 static const MCOperandInfo OperandInfo105[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
5418 static const MCOperandInfo OperandInfo106[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5418 static const MCOperandInfo OperandInfo106[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5419 static const MCOperandInfo OperandInfo107[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5419 static const MCOperandInfo OperandInfo107[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5419 static const MCOperandInfo OperandInfo107[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5420 static const MCOperandInfo OperandInfo108[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5421 static const MCOperandInfo OperandInfo109[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
5494 static const MCOperandInfo OperandInfo182[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5495 static const MCOperandInfo OperandInfo183[] = { { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
5497 static const MCOperandInfo OperandInfo185[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5498 static const MCOperandInfo OperandInfo186[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5498 static const MCOperandInfo OperandInfo186[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5507 static const MCOperandInfo OperandInfo195[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5514 static const MCOperandInfo OperandInfo202[] = { { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5518 static const MCOperandInfo OperandInfo206[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5520 static const MCOperandInfo OperandInfo208[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5523 static const MCOperandInfo OperandInfo211[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
5523 static const MCOperandInfo OperandInfo211[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
5525 static const MCOperandInfo OperandInfo213[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
5525 static const MCOperandInfo OperandInfo213[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
5530 static const MCOperandInfo OperandInfo218[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5531 static const MCOperandInfo OperandInfo219[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5531 static const MCOperandInfo OperandInfo219[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5534 static const MCOperandInfo OperandInfo222[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5534 static const MCOperandInfo OperandInfo222[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5539 static const MCOperandInfo OperandInfo227[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5540 static const MCOperandInfo OperandInfo228[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5540 static const MCOperandInfo OperandInfo228[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5541 static const MCOperandInfo OperandInfo229[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5541 static const MCOperandInfo OperandInfo229[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5542 static const MCOperandInfo OperandInfo230[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5550 static const MCOperandInfo OperandInfo238[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5551 static const MCOperandInfo OperandInfo239[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5554 static const MCOperandInfo OperandInfo242[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5554 static const MCOperandInfo OperandInfo242[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5556 static const MCOperandInfo OperandInfo244[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5556 static const MCOperandInfo OperandInfo244[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5558 static const MCOperandInfo OperandInfo246[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5558 static const MCOperandInfo OperandInfo246[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5562 static const MCOperandInfo OperandInfo250[] = { { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
5642 static const MCOperandInfo OperandInfo330[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5645 static const MCOperandInfo OperandInfo333[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5652 static const MCOperandInfo OperandInfo340[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5657 static const MCOperandInfo OperandInfo345[] = { { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5687 static const MCOperandInfo OperandInfo375[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5688 static const MCOperandInfo OperandInfo376[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5728 static const MCOperandInfo OperandInfo416[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5735 static const MCOperandInfo OperandInfo423[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5740 static const MCOperandInfo OperandInfo428[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5759 static const MCOperandInfo OperandInfo447[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5759 static const MCOperandInfo OperandInfo447[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5760 static const MCOperandInfo OperandInfo448[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5760 static const MCOperandInfo OperandInfo448[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5760 static const MCOperandInfo OperandInfo448[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5761 static const MCOperandInfo OperandInfo449[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5761 static const MCOperandInfo OperandInfo449[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5761 static const MCOperandInfo OperandInfo449[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5764 static const MCOperandInfo OperandInfo452[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5765 static const MCOperandInfo OperandInfo453[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5766 static const MCOperandInfo OperandInfo454[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5767 static const MCOperandInfo OperandInfo455[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5767 static const MCOperandInfo OperandInfo455[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5767 static const MCOperandInfo OperandInfo455[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5769 static const MCOperandInfo OperandInfo457[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5771 static const MCOperandInfo OperandInfo459[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5771 static const MCOperandInfo OperandInfo459[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5772 static const MCOperandInfo OperandInfo460[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5773 static const MCOperandInfo OperandInfo461[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5774 static const MCOperandInfo OperandInfo462[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
5774 static const MCOperandInfo OperandInfo462[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
5774 static const MCOperandInfo OperandInfo462[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
5775 static const MCOperandInfo OperandInfo463[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
5776 static const MCOperandInfo OperandInfo464[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5777 static const MCOperandInfo OperandInfo465[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5777 static const MCOperandInfo OperandInfo465[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5778 static const MCOperandInfo OperandInfo466[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5779 static const MCOperandInfo OperandInfo467[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5780 static const MCOperandInfo OperandInfo468[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5780 static const MCOperandInfo OperandInfo468[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5781 static const MCOperandInfo OperandInfo469[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5781 static const MCOperandInfo OperandInfo469[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5782 static const MCOperandInfo OperandInfo470[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5783 static const MCOperandInfo OperandInfo471[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5785 static const MCOperandInfo OperandInfo473[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5785 static const MCOperandInfo OperandInfo473[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5785 static const MCOperandInfo OperandInfo473[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5785 static const MCOperandInfo OperandInfo473[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5786 static const MCOperandInfo OperandInfo474[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5789 static const MCOperandInfo OperandInfo477[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5790 static const MCOperandInfo OperandInfo478[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5790 static const MCOperandInfo OperandInfo478[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5790 static const MCOperandInfo OperandInfo478[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5791 static const MCOperandInfo OperandInfo479[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5791 static const MCOperandInfo OperandInfo479[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5792 static const MCOperandInfo OperandInfo480[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5792 static const MCOperandInfo OperandInfo480[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5793 static const MCOperandInfo OperandInfo481[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5793 static const MCOperandInfo OperandInfo481[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5793 static const MCOperandInfo OperandInfo481[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5795 static const MCOperandInfo OperandInfo483[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5796 static const MCOperandInfo OperandInfo484[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5796 static const MCOperandInfo OperandInfo484[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5797 static const MCOperandInfo OperandInfo485[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5797 static const MCOperandInfo OperandInfo485[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5797 static const MCOperandInfo OperandInfo485[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5797 static const MCOperandInfo OperandInfo485[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5797 static const MCOperandInfo OperandInfo485[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5797 static const MCOperandInfo OperandInfo485[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5798 static const MCOperandInfo OperandInfo486[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5798 static const MCOperandInfo OperandInfo486[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5799 static const MCOperandInfo OperandInfo487[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5799 static const MCOperandInfo OperandInfo487[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5800 static const MCOperandInfo OperandInfo488[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5800 static const MCOperandInfo OperandInfo488[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5801 static const MCOperandInfo OperandInfo489[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5801 static const MCOperandInfo OperandInfo489[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5801 static const MCOperandInfo OperandInfo489[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5802 static const MCOperandInfo OperandInfo490[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5803 static const MCOperandInfo OperandInfo491[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5803 static const MCOperandInfo OperandInfo491[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5804 static const MCOperandInfo OperandInfo492[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5804 static const MCOperandInfo OperandInfo492[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5805 static const MCOperandInfo OperandInfo493[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5805 static const MCOperandInfo OperandInfo493[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5807 static const MCOperandInfo OperandInfo495[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5808 static const MCOperandInfo OperandInfo496[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
gen/lib/Target/ARM/ARMGenRegisterBank.inc 63 (1u << (ARM::rGPRRegClassID - 0)) |
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 2902 { rGPR, rGPRBits, 1523, 14, sizeof(rGPRBits), ARM::rGPRRegClassID, 1, true },
6036 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::rGPRRegClassID];
6678 &ARMMCRegisterClasses[rGPRRegClassID],
lib/Target/ARM/ARMRegisterBankInfo.cpp 155 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
183 case rGPRRegClassID:
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 1405 if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(
10268 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {