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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenDAGISel.inc25006 /* 53887*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25021 /* 53929*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25036 /* 53971*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25051 /* 54013*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25076 /* 54071*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25091 /* 54113*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25106 /* 54155*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25121 /* 54197*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25146 /* 54255*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25161 /* 54297*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25176 /* 54339*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25191 /* 54381*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25216 /* 54439*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25231 /* 54481*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25246 /* 54523*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25261 /* 54565*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25286 /* 54623*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25301 /* 54665*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25316 /* 54707*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
25331 /* 54749*/ OPC_EmitInteger, MVT::i32, ARM::qsub_3,
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 8444 { ARM::dsub_4, ARM::dsub_5, ARM::dsub_6, ARM::dsub_7, 0, 0, 0, 0, 0, 0, 0, 0, ARM::qsub_2, ARM::qsub_3, 0, 0, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, ARM::ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, ARM::dsub_5_dsub_7, ARM::dsub_5_ssub_12_ssub_13_dsub_7, ARM::dsub_5_ssub_12_ssub_13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8445 { ARM::dsub_5, ARM::dsub_6, ARM::dsub_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, ARM::dsub_5_ssub_12_ssub_13, 0, 0, 0, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ARM::dsub_5_dsub_7, 0, 0, 0, ARM::qsub_3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
lib/Target/ARM/ARMISelDAGToDAG.cpp 1771 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, dl, MVT::i32);
2048 ARM::qsub_3 == ARM::qsub_0 + 3,
2326 ARM::qsub_3 == ARM::qsub_0 + 3,