|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenDAGISel.inc25005 /* 53884*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25020 /* 53926*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25035 /* 53968*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25050 /* 54010*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25075 /* 54068*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25090 /* 54110*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25105 /* 54152*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25120 /* 54194*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25145 /* 54252*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25160 /* 54294*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25175 /* 54336*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25190 /* 54378*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25215 /* 54436*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25230 /* 54478*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25245 /* 54520*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25260 /* 54562*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25285 /* 54620*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25300 /* 54662*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25315 /* 54704*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
25330 /* 54746*/ OPC_EmitInteger, MVT::i32, ARM::qsub_2,
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 8442 { ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, ARM::dsub_5, ARM::dsub_6, 0, 0, 0, 0, 0, 0, 0, ARM::qsub_1, ARM::qsub_2, 0, 0, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, 0, 0, 0, 0, 0, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9, ARM::ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, ARM::ssub_6_ssub_7_dsub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8443 { ARM::dsub_3, ARM::dsub_4, ARM::dsub_5, ARM::dsub_6, ARM::dsub_7, 0, 0, 0, 0, 0, 0, 0, ARM::ssub_6_ssub_7_ssub_8_ssub_9, ARM::dsub_5_ssub_12_ssub_13, 0, 0, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, ARM::ssub_6_ssub_7_dsub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, ARM::ssub_8_ssub_9_ssub_12_ssub_13, ARM::ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, ARM::qsub_2, 0, 0, 0, 0, 0, ARM::dsub_5_dsub_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8444 { ARM::dsub_4, ARM::dsub_5, ARM::dsub_6, ARM::dsub_7, 0, 0, 0, 0, 0, 0, 0, 0, ARM::qsub_2, ARM::qsub_3, 0, 0, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, ARM::ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, ARM::dsub_5_dsub_7, ARM::dsub_5_ssub_12_ssub_13_dsub_7, ARM::dsub_5_ssub_12_ssub_13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
lib/Target/ARM/ARMISelDAGToDAG.cpp 1770 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, dl, MVT::i32);