reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenDAGISel.inc
24834 /* 53498*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
24847 /* 53530*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
24866 /* 53571*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
24879 /* 53603*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
24898 /* 53644*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
24911 /* 53676*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
24930 /* 53717*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
24943 /* 53749*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
24962 /* 53790*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
24975 /* 53822*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25004 /* 53881*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25019 /* 53923*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25034 /* 53965*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25049 /* 54007*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25074 /* 54065*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25089 /* 54107*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25104 /* 54149*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25119 /* 54191*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25144 /* 54249*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25159 /* 54291*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25174 /* 54333*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25189 /* 54375*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25214 /* 54433*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25229 /* 54475*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25244 /* 54517*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25259 /* 54559*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25284 /* 54617*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25299 /* 54659*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25314 /* 54701*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
25329 /* 54743*/          OPC_EmitInteger, MVT::i32, ARM::qsub_1,
gen/lib/Target/ARM/ARMGenRegisterInfo.inc
 8440     { ARM::dsub_0, ARM::dsub_1, ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, 0, ARM::dsub_6, 0, 0, 0, 0, 0, ARM::qsub_0, ARM::qsub_1, 0, 0, ARM::ssub_0, ARM::ssub_1, ARM::ssub_2, ARM::ssub_3, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, 0, 0, ARM::ssub_12, ARM::ssub_13, 0, 0, ARM::ssub_0_ssub_1_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_2_ssub_3_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, 0, 0, 0, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, },
 8441     { ARM::dsub_1, ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, ARM::dsub_5, 0, ARM::dsub_7, 0, 0, 0, 0, 0, ARM::ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9, 0, 0, ARM::ssub_2, ARM::ssub_3, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, 0, 0, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, ARM::ssub_2_ssub_3_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, ARM::ssub_4_ssub_5_ssub_8_ssub_9, ARM::ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, ARM::qsub_1, ARM::ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, 0, 0, 0, 0, ARM::ssub_6_ssub_7_dsub_5, 0, ARM::ssub_6_ssub_7_dsub_5_dsub_7, 0, 0, 0, 0, 0, ARM::dsub_5_dsub_7, 0, 0, 0, 0, 0, },
 8442     { ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, ARM::dsub_5, ARM::dsub_6, 0, 0, 0, 0, 0, 0, 0, ARM::qsub_1, ARM::qsub_2, 0, 0, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, 0, 0, 0, 0, 0, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9, ARM::ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, ARM::ssub_6_ssub_7_dsub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
lib/Target/ARM/ARMISelDAGToDAG.cpp
 1727   SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32);
 1769   SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32);