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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenDAGISel.inc24833 /* 53495*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
24846 /* 53527*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
24865 /* 53568*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
24878 /* 53600*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
24897 /* 53641*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
24910 /* 53673*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
24929 /* 53714*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
24942 /* 53746*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
24961 /* 53787*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
24974 /* 53819*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25003 /* 53878*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25018 /* 53920*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25033 /* 53962*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25048 /* 54004*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25073 /* 54062*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25088 /* 54104*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25103 /* 54146*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25118 /* 54188*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25143 /* 54246*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25158 /* 54288*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25173 /* 54330*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25188 /* 54372*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25213 /* 54430*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25228 /* 54472*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25243 /* 54514*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25258 /* 54556*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25283 /* 54614*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25298 /* 54656*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25313 /* 54698*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
25328 /* 54740*/ OPC_EmitInteger, MVT::i32, ARM::qsub_0,
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 8440 { ARM::dsub_0, ARM::dsub_1, ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, 0, ARM::dsub_6, 0, 0, 0, 0, 0, ARM::qsub_0, ARM::qsub_1, 0, 0, ARM::ssub_0, ARM::ssub_1, ARM::ssub_2, ARM::ssub_3, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, 0, 0, ARM::ssub_12, ARM::ssub_13, 0, 0, ARM::ssub_0_ssub_1_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_2_ssub_3_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, 0, 0, 0, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, },
lib/Target/ARM/ARMBaseInstrInfo.cpp 880 BeginIdx = ARM::qsub_0;
884 BeginIdx = ARM::qsub_0;
lib/Target/ARM/ARMISelDAGToDAG.cpp 1726 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32);
1768 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32);
2048 ARM::qsub_3 == ARM::qsub_0 + 3,
2050 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
2326 ARM::qsub_3 == ARM::qsub_0 + 3,
2328 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2496 CurDAG->getTargetExtractSubreg(ARM::qsub_0 + i, Loc, VT, Data));
2621 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp 1633 printRegName(O, MRI.getSubReg(Reg, ARM::qsub_0 + i));