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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenDAGISel.inc21068 /* 45205*/ OPC_EmitInteger, MVT::i32, ARM::dsub_1,
21087 /* 45253*/ OPC_EmitInteger, MVT::i32, ARM::dsub_1,
21109 /* 45311*/ OPC_EmitInteger, MVT::i32, ARM::dsub_1,
21129 /* 45368*/ OPC_EmitInteger, MVT::i32, ARM::dsub_1,
21152 /* 45431*/ OPC_EmitInteger, MVT::i32, ARM::dsub_1,
53270 /*119049*/ OPC_EmitInteger, MVT::i32, ARM::dsub_1,
53279 /*119073*/ OPC_EmitInteger, MVT::i32, ARM::dsub_1,
53288 /*119097*/ OPC_EmitInteger, MVT::i32, ARM::dsub_1,
53297 /*119121*/ OPC_EmitInteger, MVT::i32, ARM::dsub_1,
53306 /*119145*/ OPC_EmitInteger, MVT::i32, ARM::dsub_1,
53315 /*119169*/ OPC_EmitInteger, MVT::i32, ARM::dsub_1,
53759 /*120342*/ OPC_EmitInteger, MVT::i32, ARM::dsub_1,
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 8440 { ARM::dsub_0, ARM::dsub_1, ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, 0, ARM::dsub_6, 0, 0, 0, 0, 0, ARM::qsub_0, ARM::qsub_1, 0, 0, ARM::ssub_0, ARM::ssub_1, ARM::ssub_2, ARM::ssub_3, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, 0, 0, ARM::ssub_12, ARM::ssub_13, 0, 0, ARM::ssub_0_ssub_1_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_2_ssub_3_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, 0, 0, 0, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, },
8441 { ARM::dsub_1, ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, ARM::dsub_5, 0, ARM::dsub_7, 0, 0, 0, 0, 0, ARM::ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9, 0, 0, ARM::ssub_2, ARM::ssub_3, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, 0, 0, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, ARM::ssub_2_ssub_3_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, ARM::ssub_4_ssub_5_ssub_8_ssub_9, ARM::ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, ARM::qsub_1, ARM::ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, 0, 0, 0, 0, ARM::ssub_6_ssub_7_dsub_5, 0, ARM::ssub_6_ssub_7_dsub_5_dsub_7, 0, 0, 0, 0, 0, ARM::dsub_5_dsub_7, 0, 0, 0, 0, 0, },
lib/Target/ARM/A15SDOptimizer.cpp 459 .addImm(ARM::dsub_1);
523 ARM::dsub_1, &ARM::DPRRegClass);
lib/Target/ARM/ARMAsmPrinter.cpp 408 TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1);
lib/Target/ARM/ARMBaseInstrInfo.cpp 1151 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1176 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1190 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1386 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1409 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1425 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
lib/Target/ARM/ARMExpandPseudoInsts.cpp 440 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
460 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
493 SubRegIndex = ARM::dsub_1;
1605 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1637 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
lib/Target/ARM/ARMISelDAGToDAG.cpp 1716 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32);
1754 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32);
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp 1437 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1505 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);