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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenDAGISel.inc16769 /* 35858*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
16848 /* 36007*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
21067 /* 45202*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
21086 /* 45250*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
21108 /* 45308*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
21128 /* 45365*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
21151 /* 45428*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28482 /* 61769*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28505 /* 61835*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28528 /* 61901*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28551 /* 61967*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28574 /* 62033*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28597 /* 62099*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28620 /* 62165*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28648 /* 62249*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28676 /* 62333*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28704 /* 62417*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28732 /* 62501*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28760 /* 62585*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28792 /* 62684*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28819 /* 62765*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28846 /* 62846*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28873 /* 62927*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28900 /* 63008*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28927 /* 63089*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28950 /* 63155*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28957 /* 63181*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28980 /* 63247*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
28987 /* 63273*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29010 /* 63339*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29017 /* 63365*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29044 /* 63446*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29076 /* 63545*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29108 /* 63644*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29140 /* 63743*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29172 /* 63842*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29204 /* 63941*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29236 /* 64040*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29243 /* 64066*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29270 /* 64147*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29277 /* 64173*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29304 /* 64254*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29311 /* 64280*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29334 /* 64346*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29341 /* 64372*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29369 /* 64456*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29376 /* 64482*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29404 /* 64566*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29411 /* 64592*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29443 /* 64691*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29450 /* 64717*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29482 /* 64816*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29489 /* 64842*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29521 /* 64941*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
29528 /* 64967*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
49286 /*109690*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
49295 /*109712*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
49304 /*109734*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
49313 /*109756*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
49322 /*109778*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
49331 /*109800*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
53269 /*119046*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
53278 /*119070*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
53287 /*119094*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
53296 /*119118*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
53305 /*119142*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
53314 /*119166*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
53610 /*119970*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
53639 /*120050*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
53668 /*120130*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
53735 /*120290*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
53758 /*120339*/ OPC_EmitInteger, MVT::i32, ARM::dsub_0,
55064 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
55065 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, SDLoc(N),
55078 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
55079 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, SDLoc(N),
55135 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
55136 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, SDLoc(N),
55165 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
55166 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), SDLoc(N),
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 8440 { ARM::dsub_0, ARM::dsub_1, ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, 0, ARM::dsub_6, 0, 0, 0, 0, 0, ARM::qsub_0, ARM::qsub_1, 0, 0, ARM::ssub_0, ARM::ssub_1, ARM::ssub_2, ARM::ssub_3, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, 0, 0, ARM::ssub_12, ARM::ssub_13, 0, 0, ARM::ssub_0_ssub_1_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_2_ssub_3_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, 0, 0, 0, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, },
lib/Target/ARM/A15SDOptimizer.cpp 457 .addImm(ARM::dsub_0)
521 ARM::dsub_0, &ARM::DPRRegClass);
lib/Target/ARM/ARMAsmPrinter.cpp 408 TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1);
lib/Target/ARM/ARMBaseInstrInfo.cpp 889 BeginIdx = ARM::dsub_0;
893 BeginIdx = ARM::dsub_0;
897 BeginIdx = ARM::dsub_0;
905 BeginIdx = ARM::dsub_0;
910 BeginIdx = ARM::dsub_0;
915 BeginIdx = ARM::dsub_0;
1150 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1175 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1189 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1385 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1408 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1424 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
lib/Target/ARM/ARMExpandPseudoInsts.cpp 439 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
454 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
490 SubRegIndex = ARM::dsub_0;
496 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0,
1604 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1636 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
lib/Target/ARM/ARMFrameLowering.cpp 1241 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1260 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1275 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1373 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1391 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1404 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
lib/Target/ARM/ARMISelDAGToDAG.cpp 1715 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32);
1753 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32);
2047 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 &&
2050 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
2325 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 &&
2328 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2620 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7, "Unexpected subreg numbering");
2621 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 302 return MRI->getSubReg(QReg, ARM::dsub_0);
4534 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
4539 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
4732 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp 1436 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1449 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1504 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1551 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);