reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/ARM/ARMGenRegisterInfo.inc

 3603   extern const TargetRegisterClass SPRRegClass;

References

gen/lib/Target/ARM/ARMGenFastISel.inc

  153     return fastEmitInst_r(ARM::VCMPZS, &ARM::SPRRegClass, Op0, Op0IsKill);
  332     return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill);
  734     return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill);
 1760     return fastEmitInst_r(ARM::VABSS, &ARM::SPRRegClass, Op0, Op0IsKill);
 1844     return fastEmitInst_r(ARM::VRINTPS, &ARM::SPRRegClass, Op0, Op0IsKill);
 1902     return fastEmitInst_r(ARM::VRINTMS, &ARM::SPRRegClass, Op0, Op0IsKill);
 1960     return fastEmitInst_r(ARM::VRINTRS, &ARM::SPRRegClass, Op0, Op0IsKill);
 1998     return fastEmitInst_r(ARM::VNEGS, &ARM::SPRRegClass, Op0, Op0IsKill);
 2091     return fastEmitInst_r(ARM::VCVTSD, &ARM::SPRRegClass, Op0, Op0IsKill);
 2226     return fastEmitInst_r(ARM::VRINTXS, &ARM::SPRRegClass, Op0, Op0IsKill);
 2284     return fastEmitInst_r(ARM::VRINTAS, &ARM::SPRRegClass, Op0, Op0IsKill);
 2342     return fastEmitInst_r(ARM::VSQRTS, &ARM::SPRRegClass, Op0, Op0IsKill);
 2380     return fastEmitInst_r(ARM::VRINTZS, &ARM::SPRRegClass, Op0, Op0IsKill);
 2773     return fastEmitInst_rr(ARM::VCMPS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3603     return fastEmitInst_rr(ARM::VADDS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3687     return fastEmitInst_rr(ARM::VDIVS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3773     return fastEmitInst_rr(ARM::VFP_VMAXNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3905     return fastEmitInst_rr(ARM::VFP_VMINNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3989     return fastEmitInst_rr(ARM::VMULS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4073     return fastEmitInst_rr(ARM::VSUBS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);

gen/lib/Target/ARM/ARMGenRegisterInfo.inc

 4919   &ARM::SPRRegClass,
 8015     &ARM::SPRRegClass,

lib/Target/ARM/A15SDOptimizer.cpp

  165                                     &ARM::SPRRegClass)) {
  289                                           &ARM::SPRRegClass)) {
  327   if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
  331                                            &ARM::SPRRegClass))
  334   if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
  541     assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&

lib/Target/ARM/ARMBaseInstrInfo.cpp

  845   bool SPRDest = ARM::SPRRegClass.contains(DestReg);
  846   bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
 1060       } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
 1300     } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
 1592   if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
 5182   } else if (ARM::SPRRegClass.contains(Reg)) {
 5209   if (ARM::SPRRegClass.contains(Reg)) {

lib/Target/ARM/ARMFastISel.cpp

 1529   unsigned Result = createResultReg(&ARM::SPRRegClass);

lib/Target/ARM/ARMFrameLowering.cpp

 1715         if (ARM::SPRRegClass.contains(Reg))

lib/Target/ARM/ARMISelLowering.cpp

  693     addRegisterClass(MVT::f32, &ARM::SPRRegClass);
 4057           RC = &ARM::SPRRegClass;
15697         return RCPair(0U, &ARM::SPRRegClass);
15717         return RCPair(0U, &ARM::SPRRegClass);

lib/Target/ARM/ARMInstructionSelector.cpp

  198       return &ARM::SPRRegClass;