|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 9082 case ARM::R4: OpKind = MCK_Reg12; break;
gen/lib/Target/ARM/ARMGenCallingConv.inc 486 ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5300 static const MCPhysReg ImplicitList5[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
5301 static const MCPhysReg ImplicitList6[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, 0 };
5303 static const MCPhysReg ImplicitList8[] = { ARM::R4, 0 };
5304 static const MCPhysReg ImplicitList9[] = { ARM::R4, ARM::SP, 0 };
5310 static const MCPhysReg ImplicitList15[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
5312 static const MCPhysReg ImplicitList17[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::CPSR, 0 };
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 1553 { ARM::R4 },
1607 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
1617 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV,
1627 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::ZR,
1647 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
1657 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::APSR,
1667 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::ZR,
1677 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
1687 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC,
1717 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1727 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, ARM::R12, ARM::LR,
1787 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
3021 { 4U, ARM::R4 },
3073 { 4U, ARM::R4 },
3161 { ARM::R4, 4U },
3214 { ARM::R4, 4U },
5939 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::PC };
5940 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5941 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC };
5959 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5960 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5977 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::ZR };
5978 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5995 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5996 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5997 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP };
6015 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::ZR };
6016 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
6033 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12 };
6034 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
6035 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11 };
6053 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R6 };
6101 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R6 };
16003 static const MCPhysReg CSR_AAPCS_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16005 static const MCPhysReg CSR_AAPCS_SplitPush_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16007 static const MCPhysReg CSR_AAPCS_SplitPush_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16009 static const MCPhysReg CSR_AAPCS_SwiftError_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16011 static const MCPhysReg CSR_AAPCS_ThisReturn_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 };
16013 static const MCPhysReg CSR_FIQ_SaveList[] = { ARM::LR, ARM::R11, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
16017 static const MCPhysReg CSR_GenericInt_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
16021 static const MCPhysReg CSR_Win_AAPCS_CFGuard_Check_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
16023 static const MCPhysReg CSR_iOS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16025 static const MCPhysReg CSR_iOS_CXX_TLS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R12, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
16027 static const MCPhysReg CSR_iOS_CXX_TLS_PE_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R7, ARM::R5, ARM::R4, 0 };
16031 static const MCPhysReg CSR_iOS_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16033 static const MCPhysReg CSR_iOS_TLSCall_SaveList[] = { ARM::LR, ARM::SP, ARM::R11, ARM::R10, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
16035 static const MCPhysReg CSR_iOS_ThisReturn_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 };
lib/Target/ARM/ARMBaseRegisterInfo.h 48 case R4: case R5: case R6: case R7:
lib/Target/ARM/ARMFrameLowering.cpp 433 case ARM::R4:
522 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
527 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
540 .addReg(ARM::R4, RegState::Implicit)
551 .addReg(ARM::R4, RegState::Implicit)
558 .addReg(ARM::R4, RegState::Kill)
640 case ARM::R4:
733 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
736 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign,
739 .addReg(ARM::R4, RegState::Kill)
831 assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
833 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
836 .addReg(ARM::R4)
1209 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1221 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);
1229 .addReg(ARM::R4)
1244 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4)
1245 .addReg(ARM::R4, RegState::Kill)
1264 .addReg(ARM::R4)
1279 .addReg(ARM::R4)
1293 .addReg(ARM::R4)
1299 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1326 assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
1362 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1376 .addReg(ARM::R4, RegState::Define)
1377 .addReg(ARM::R4, RegState::Kill)
1394 .addReg(ARM::R4)
1407 .addReg(ARM::R4)
1417 .addReg(ARM::R4)
1422 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1630 SavedRegs.set(ARM::R4);
1666 SavedRegs.set(ARM::R4);
1675 SavedRegs.set(ARM::R4);
1692 SavedRegs.set(ARM::R4);
1742 case ARM::R4: case ARM::R5:
1758 case ARM::R4: case ARM::R5:
1945 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) {
2284 unsigned ScratchReg0 = ARM::R4;
lib/Target/ARM/ARMISelLowering.cpp 2464 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2471 unsigned Excess = 4 * (ARM::R4 - Reg);
2491 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
3901 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
3902 REnd = ARM::R4;
3906 ArgOffset = -4 * (ARM::R4 - RBegin);
3981 unsigned ArgRegBegin = ARM::R4;
4008 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
10292 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
10293 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
10308 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
10309 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
10320 .addReg(ARM::R4, RegState::Kill)
16087 Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag);
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 3909 .Case("v1", ARM::R4)
4252 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
4253 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 1115 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1122 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp 1211 {ARM::R4, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R4},
lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h 164 case R4: case R5: case R6: case R7:
lib/Target/ARM/Thumb1FrameLowering.cpp 219 case ARM::R4:
284 case ARM::R4:
412 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
416 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4)
418 .addReg(ARM::R4, RegState::Kill)
422 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4)
424 .addReg(ARM::R4, RegState::Kill)
429 .addReg(ARM::R4, RegState::Kill)
515 assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
517 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
520 .addReg(ARM::R4)
853 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
875 ARM::R5, ARM::R4, ARM::R3,
985 ARM::R4, ARM::R5, ARM::R6, ARM::R7};