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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 9079 case ARM::R1: OpKind = MCK_Reg15; break;
gen/lib/Target/ARM/ARMGenCallingConv.inc 143 ARM::R0, ARM::R1
155 ARM::R0, ARM::R1, ARM::R2, ARM::R3
167 ARM::R0, ARM::R1, ARM::R2, ARM::R3
177 ARM::R0, ARM::R1, ARM::R2, ARM::R3
389 ARM::R0, ARM::R1, ARM::R2, ARM::R3
681 ARM::R0, ARM::R1, ARM::R2, ARM::R3
694 ARM::R1, ARM::R3
854 ARM::R0, ARM::R1, ARM::R2, ARM::R3
867 ARM::R1, ARM::R3
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5300 static const MCPhysReg ImplicitList5[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
5301 static const MCPhysReg ImplicitList6[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, 0 };
5310 static const MCPhysReg ImplicitList15[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
5312 static const MCPhysReg ImplicitList17[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::CPSR, 0 };
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 1550 { ARM::R1 },
1607 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
1617 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV,
1627 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::ZR,
1647 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
1657 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::APSR,
1667 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::ZR,
1677 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
1687 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC,
1717 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1757 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
1767 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12,
1797 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
1807 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1847 ARM::R1, ARM::R3,
3018 { 1U, ARM::R1 },
3070 { 1U, ARM::R1 },
3158 { ARM::R1, 1U },
3211 { ARM::R1, 1U },
5939 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::PC };
5940 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5941 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC };
5959 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5960 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5977 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::ZR };
5978 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5995 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5996 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5997 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP };
6015 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::ZR };
6016 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
6033 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12 };
6034 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
6035 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11 };
6069 static const MCPhysReg AltOrder1[] = { ARM::R1, ARM::R3, ARM::R5, ARM::R7 };
6085 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
6117 static const MCPhysReg AltOrder1[] = { ARM::R1, ARM::R3, ARM::R5, ARM::R7 };
6133 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
6196 static const MCPhysReg AltOrder1[] = { ARM::R1, ARM::R3 };
16013 static const MCPhysReg CSR_FIQ_SaveList[] = { ARM::LR, ARM::R11, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
16017 static const MCPhysReg CSR_GenericInt_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
16025 static const MCPhysReg CSR_iOS_CXX_TLS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R12, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
16029 static const MCPhysReg CSR_iOS_CXX_TLS_ViaCopy_SaveList[] = { ARM::R6, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
16033 static const MCPhysReg CSR_iOS_TLSCall_SaveList[] = { ARM::LR, ARM::SP, ARM::R11, ARM::R10, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
lib/Target/ARM/ARMBaseRegisterInfo.h 47 case R0: case R1: case R2: case R3:
lib/Target/ARM/ARMCallingConv.cpp 24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
68 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
69 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
70 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
120 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
156 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
lib/Target/ARM/ARMFastISel.cpp 3052 ARM::R0, ARM::R1, ARM::R2, ARM::R3
lib/Target/ARM/ARMFrameLowering.cpp 430 case ARM::R1:
637 case ARM::R1:
1740 case ARM::R0: case ARM::R1:
1756 case ARM::R0: case ARM::R1:
1924 for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) {
lib/Target/ARM/ARMISelLowering.cpp 147 ARM::R0, ARM::R1, ARM::R2, ARM::R3
17086 return Subtarget->useSjLjEH() ? ARM::NoRegister : ARM::R1;
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 3906 .Case("a2", ARM::R1)
4251 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
4251 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 1114 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1121 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1242 Register = ARM::R1;
lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h 163 case R0: case R1: case R2: case R3:
lib/Target/ARM/Thumb1FrameLowering.cpp 281 case ARM::R1:
844 for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
876 ARM::R2, ARM::R1, ARM::R0};
975 CopyRegs[ARM::R1] = true;
984 static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,