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reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc
 9093     case ARM::PC: OpKind = MCK_PC; break;
gen/lib/Target/ARM/ARMGenInstrInfo.inc
 5305 static const MCPhysReg ImplicitList10[] = { ARM::PC, 0 };
gen/lib/Target/ARM/ARMGenMCPseudoLowering.inc
   84       TmpInst.addOperand(MCOperand::createReg(ARM::PC));
  208       TmpInst.addOperand(MCOperand::createReg(ARM::PC));
  340       TmpInst.addOperand(MCOperand::createReg(ARM::PC));
gen/lib/Target/ARM/ARMGenRegisterInfo.inc
 1491   { ARM::PC },
 1607     ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 
 1687     ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC, 
 1707     ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 
 1907     ARM::PC, 
 3122   { ARM::PC, 15U },
 3175   { ARM::PC, 15U },
 5939   static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::PC };
 5941   static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC };
lib/Target/ARM/ARMAsmPrinter.cpp
 1307       .addReg(ARM::PC)
 1353       .addReg(ARM::PC)
 1361       .addReg(ARM::PC)
 1373       .addReg(ARM::PC)
 1530       .addReg(ARM::PC)
 1550       .addReg(ARM::PC)
 1594       .addReg(ARM::PC)
 1642       .addReg(ARM::PC)
 1681     if (Base == ARM::PC) {
 1739                                      .addReg(ARM::PC)
 1740                                      .addReg(ARM::PC)
 1754     TmpInst.addOperand(MCOperand::createReg(ARM::PC));
 1769     TmpInst.addOperand(MCOperand::createReg(ARM::PC));
 1782     TmpInst.addOperand(MCOperand::createReg(ARM::PC));
 1795       .addReg(ARM::PC)
 1853       .addReg(ARM::PC)
 1919       .addReg(ARM::PC)
 1945       .addReg(ARM::PC)
 1946       .addReg(ARM::PC)
 2115                                      .addReg(ARM::PC)
lib/Target/ARM/ARMBaseInstrInfo.cpp
 4755             !(MI.getOpcode() == ARM::tPOP_RET && Reg == ARM::PC)) {
lib/Target/ARM/ARMBaseRegisterInfo.cpp
   58     : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
  194   markSuperRegs(Reserved, ARM::PC);
lib/Target/ARM/ARMBaseRegisterInfo.h
   49     case LR:  case SP:  case PC:
lib/Target/ARM/ARMConstantIslandPass.cpp
 1747         MI->getOperand(2).getReg() == ARM::PC &&
 2308       NewJTMI->getOperand(0).setReg(ARM::PC);
lib/Target/ARM/ARMExpandPseudoInsts.cpp
 1576           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
lib/Target/ARM/ARMFeatures.h
   78     return Instr->getOperand(2).getReg() != ARM::PC;
   83     return Instr->getOperand(0).getReg() != ARM::PC;
   85     return Instr->getOperand(0).getReg() != ARM::PC &&
   86            Instr->getOperand(2).getReg() != ARM::PC;
   89     return Instr->getOperand(0).getReg() != ARM::PC &&
   90            Instr->getOperand(1).getReg() != ARM::PC;
lib/Target/ARM/ARMFrameLowering.cpp
 1091           Reg = ARM::PC;
 1135       if (Regs[0] == ARM::PC)
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
 1030     if (PReg == ARM::SP || PReg == ARM::PC)
 1056       if (Reg == ARM::SP || Reg == ARM::PC)
 1950       MO.setReg(ARM::PC);
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 1043       if(Memory.BaseRegNum != ARM::PC) return false;
 1429     if (Memory.BaseRegNum != ARM::PC)
 1621         Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
 1725     if (Memory.BaseRegNum == ARM::PC) return false;
 1819     if (Memory.BaseRegNum == ARM::PC) return false;
 3902       .Case("r15", ARM::PC)
 4258   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
 4258   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
 6437     bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
 6437     bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
 6438                         (Op5.isReg() && Op5.getReg() == ARM::PC);
 6556     if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
 6735   if (Op2.getReg() == ARM::PC)
 6738   if (!PairedReg || PairedReg == ARM::PC ||
 7135       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
 7193   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
 7211   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
 7629     if (!listContainsReg(Inst, 3, ARM::PC))
 7663     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
 8286     if (Inst.getOperand(1).getReg() != ARM::PC ||
 8363         Inst.getOperand(0).getReg() != ARM::PC &&
 9923     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
10286       else if (Reg == ARM::PC)
10314   if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI))
11405   if (SPReg == ARM::SP || SPReg == ARM::PC)
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 1117   ARM::R12, ARM::SP, ARM::LR, ARM::PC
lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
  143   assert((Reg != ARM::SP && Reg != ARM::PC) &&
 1423   assert((Reg != ARM::SP && Reg != ARM::PC) &&
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
 1381     PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
  991     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
 1007       Reg = ARM::PC;
 1124     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
 1353     unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
 1429     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
 1469     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
   90         MI.getOperand(OI).getReg() == ARM::PC) {
  113     case ARM::PC:
  185   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
lib/Target/ARM/Thumb1FrameLowering.cpp
  644     MIB.addReg(ARM::PC, RegState::Define);
  693   GPRsNoLRSP.reset(ARM::PC);
  758           MO.getReg() != ARM::PC) {
 1053       Reg = ARM::PC;
lib/Target/ARM/Thumb2SizeReduction.cpp
  386     if (isPCOk && Reg == ARM::PC)