|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenAsmWriter.inc12171 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12173 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(3).getReg()) &&
12186 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12188 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(3).getReg()) &&
12201 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12203 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(3).getReg()) &&
12216 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12218 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(3).getReg()) &&
12231 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12233 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(3).getReg()) &&
12246 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12248 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(3).getReg()) &&
12261 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(1).getReg()) &&
12263 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12276 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(1).getReg()) &&
12278 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12291 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(1).getReg()) &&
12293 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12306 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(1).getReg()) &&
12308 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12321 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(1).getReg()) &&
12323 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12336 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(1).getReg()) &&
12338 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12353 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(4).getReg()) &&
12355 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(5).getReg()) &&
12370 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(4).getReg()) &&
12372 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(5).getReg()) &&
12387 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(4).getReg()) &&
12389 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(5).getReg()) &&
12404 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(4).getReg()) &&
12406 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(5).getReg()) &&
12421 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12423 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(3).getReg()) &&
12438 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12440 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(3).getReg()) &&
12455 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12457 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(3).getReg()) &&
12472 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12474 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(3).getReg()) &&
12485 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(0).getReg()) &&
12487 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(1).getReg()) &&
12504 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(4).getReg()) &&
12506 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(5).getReg()) &&
12521 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(4).getReg()) &&
12523 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(5).getReg()) &&
12538 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12540 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(3).getReg()) &&
12555 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(2).getReg()) &&
12557 MRI.getRegClass(ARM::MQPRRegClassID).contains(MI->getOperand(3).getReg()) &&
gen/lib/Target/ARM/ARMGenDAGISel.inc46144 /*102282*/ OPC_EmitInteger, MVT::i32, ARM::MQPRRegClassID,
46179 /*102371*/ OPC_EmitInteger, MVT::i32, ARM::MQPRRegClassID,
gen/lib/Target/ARM/ARMGenGlobalISel.inc 2656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
2657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
2658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
3277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
3278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
3279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
3474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
3475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
3476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
4078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
4079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
4080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
4285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
4286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
4287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
4354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
4355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
4356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
4570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
4571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
4572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
4636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
4637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
4638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
4681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
4682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
4683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5674 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7212 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7645 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
9040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9041 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9054 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
9388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
9389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10976 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11116 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11117 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11512 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11622 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
21126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21210 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
21848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
21849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
21850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
24576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
24614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
25435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
25437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
25530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
25738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
25831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
26078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
26123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
27025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
27418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
27471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27472 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
27496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
27531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
27788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
27841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
27866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
27901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
28057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
28097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
28253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
28293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
28434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
28474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
28597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
28599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
28638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
28763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
28802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28897 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
28899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
28965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29172 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29587 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
29893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
30017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
30039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
30105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
30136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
30167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
30246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
30268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
30399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
30421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
30506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
30528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5383 static const MCOperandInfo OperandInfo71[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5383 static const MCOperandInfo OperandInfo71[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5498 static const MCOperandInfo OperandInfo186[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5498 static const MCOperandInfo OperandInfo186[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5499 static const MCOperandInfo OperandInfo187[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5499 static const MCOperandInfo OperandInfo187[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5499 static const MCOperandInfo OperandInfo187[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5499 static const MCOperandInfo OperandInfo187[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5500 static const MCOperandInfo OperandInfo188[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5500 static const MCOperandInfo OperandInfo188[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5500 static const MCOperandInfo OperandInfo188[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5501 static const MCOperandInfo OperandInfo189[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5501 static const MCOperandInfo OperandInfo189[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5501 static const MCOperandInfo OperandInfo189[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5501 static const MCOperandInfo OperandInfo189[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5502 static const MCOperandInfo OperandInfo190[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5502 static const MCOperandInfo OperandInfo190[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5502 static const MCOperandInfo OperandInfo190[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5502 static const MCOperandInfo OperandInfo190[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5503 static const MCOperandInfo OperandInfo191[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5504 static const MCOperandInfo OperandInfo192[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5505 static const MCOperandInfo OperandInfo193[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5506 static const MCOperandInfo OperandInfo194[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5507 static const MCOperandInfo OperandInfo195[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5507 static const MCOperandInfo OperandInfo195[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5507 static const MCOperandInfo OperandInfo195[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5508 static const MCOperandInfo OperandInfo196[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5508 static const MCOperandInfo OperandInfo196[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5509 static const MCOperandInfo OperandInfo197[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5509 static const MCOperandInfo OperandInfo197[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5509 static const MCOperandInfo OperandInfo197[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5509 static const MCOperandInfo OperandInfo197[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5510 static const MCOperandInfo OperandInfo198[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5510 static const MCOperandInfo OperandInfo198[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5510 static const MCOperandInfo OperandInfo198[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5510 static const MCOperandInfo OperandInfo198[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5511 static const MCOperandInfo OperandInfo199[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5511 static const MCOperandInfo OperandInfo199[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5511 static const MCOperandInfo OperandInfo199[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5511 static const MCOperandInfo OperandInfo199[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5512 static const MCOperandInfo OperandInfo200[] = { { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5512 static const MCOperandInfo OperandInfo200[] = { { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5513 static const MCOperandInfo OperandInfo201[] = { { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5515 static const MCOperandInfo OperandInfo203[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5515 static const MCOperandInfo OperandInfo203[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5515 static const MCOperandInfo OperandInfo203[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5516 static const MCOperandInfo OperandInfo204[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5516 static const MCOperandInfo OperandInfo204[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5516 static const MCOperandInfo OperandInfo204[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5517 static const MCOperandInfo OperandInfo205[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5517 static const MCOperandInfo OperandInfo205[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5518 static const MCOperandInfo OperandInfo206[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5518 static const MCOperandInfo OperandInfo206[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5519 static const MCOperandInfo OperandInfo207[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5519 static const MCOperandInfo OperandInfo207[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5520 static const MCOperandInfo OperandInfo208[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5520 static const MCOperandInfo OperandInfo208[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5520 static const MCOperandInfo OperandInfo208[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5521 static const MCOperandInfo OperandInfo209[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5521 static const MCOperandInfo OperandInfo209[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5521 static const MCOperandInfo OperandInfo209[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5521 static const MCOperandInfo OperandInfo209[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5526 static const MCOperandInfo OperandInfo214[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5527 static const MCOperandInfo OperandInfo215[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5528 static const MCOperandInfo OperandInfo216[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5528 static const MCOperandInfo OperandInfo216[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5529 static const MCOperandInfo OperandInfo217[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5530 static const MCOperandInfo OperandInfo218[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5531 static const MCOperandInfo OperandInfo219[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5532 static const MCOperandInfo OperandInfo220[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5532 static const MCOperandInfo OperandInfo220[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5533 static const MCOperandInfo OperandInfo221[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5533 static const MCOperandInfo OperandInfo221[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5533 static const MCOperandInfo OperandInfo221[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5534 static const MCOperandInfo OperandInfo222[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5535 static const MCOperandInfo OperandInfo223[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5535 static const MCOperandInfo OperandInfo223[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5536 static const MCOperandInfo OperandInfo224[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5536 static const MCOperandInfo OperandInfo224[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5537 static const MCOperandInfo OperandInfo225[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5537 static const MCOperandInfo OperandInfo225[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5538 static const MCOperandInfo OperandInfo226[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5538 static const MCOperandInfo OperandInfo226[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5539 static const MCOperandInfo OperandInfo227[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5540 static const MCOperandInfo OperandInfo228[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5540 static const MCOperandInfo OperandInfo228[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5541 static const MCOperandInfo OperandInfo229[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5542 static const MCOperandInfo OperandInfo230[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5542 static const MCOperandInfo OperandInfo230[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5543 static const MCOperandInfo OperandInfo231[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5543 static const MCOperandInfo OperandInfo231[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5544 static const MCOperandInfo OperandInfo232[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5544 static const MCOperandInfo OperandInfo232[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5544 static const MCOperandInfo OperandInfo232[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5544 static const MCOperandInfo OperandInfo232[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5546 static const MCOperandInfo OperandInfo234[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5546 static const MCOperandInfo OperandInfo234[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5546 static const MCOperandInfo OperandInfo234[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5547 static const MCOperandInfo OperandInfo235[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
5547 static const MCOperandInfo OperandInfo235[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
5548 static const MCOperandInfo OperandInfo236[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
5549 static const MCOperandInfo OperandInfo237[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5549 static const MCOperandInfo OperandInfo237[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5549 static const MCOperandInfo OperandInfo237[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5549 static const MCOperandInfo OperandInfo237[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5550 static const MCOperandInfo OperandInfo238[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5550 static const MCOperandInfo OperandInfo238[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5550 static const MCOperandInfo OperandInfo238[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5551 static const MCOperandInfo OperandInfo239[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5551 static const MCOperandInfo OperandInfo239[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5552 static const MCOperandInfo OperandInfo240[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5552 static const MCOperandInfo OperandInfo240[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5552 static const MCOperandInfo OperandInfo240[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5553 static const MCOperandInfo OperandInfo241[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5553 static const MCOperandInfo OperandInfo241[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5553 static const MCOperandInfo OperandInfo241[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5554 static const MCOperandInfo OperandInfo242[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5554 static const MCOperandInfo OperandInfo242[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5559 static const MCOperandInfo OperandInfo247[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5559 static const MCOperandInfo OperandInfo247[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5560 static const MCOperandInfo OperandInfo248[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5560 static const MCOperandInfo OperandInfo248[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5561 static const MCOperandInfo OperandInfo249[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5561 static const MCOperandInfo OperandInfo249[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5561 static const MCOperandInfo OperandInfo249[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
gen/lib/Target/ARM/ARMGenRegisterBank.inc 50 (1u << (ARM::MQPRRegClassID - 32)) |
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 2948 { MQPR, MQPRBits, 1581, 8, sizeof(MQPRBits), ARM::MQPRRegClassID, 1, true },
7230 &ARMMCRegisterClasses[MQPRRegClassID],
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 1295 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum))
1298 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1768 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1786 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1897 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1936 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
3173 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID];
4571 if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4615 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) ||
4652 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
unittests/Target/ARM/MachineInstrTest.cpp 496 Op.RegClass != ARM::MQPRRegClassID)