reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenDAGISel.inc
36891 /* 81164*/          OPC_EmitInteger, MVT::i32, ARM::HPRRegClassID,
36907 /* 81209*/          OPC_EmitInteger, MVT::i32, ARM::HPRRegClassID,
36948 /* 81304*/        OPC_EmitInteger, MVT::i32, ARM::HPRRegClassID,
44927 /* 99395*/        OPC_EmitInteger, MVT::i32, ARM::HPRRegClassID,
44939 /* 99426*/        OPC_EmitInteger, MVT::i32, ARM::HPRRegClassID,
gen/lib/Target/ARM/ARMGenGlobalISel.inc
11748         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
11749         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
25263       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
25264       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
25265       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
25566       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
25567       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
25568       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
25867       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
25868       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
25869       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
26160       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
26161       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
26162       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
26163       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::HPRRegClassID,
26574       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
26575       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
26576       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
26646       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
26653         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
26654         GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::HPRRegClassID,
26670         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
27056       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
27095       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
27123       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
27144       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
27200       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
27269       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
27377       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
27570       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
27639       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
27747       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
27936       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
28132       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
28328       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
28329       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
28510       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
28511       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
28512       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
28674       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
28675       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
28676       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
30207       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
30208       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
30297       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
30298       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
30360       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
30361       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
30452       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
30453       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
30557       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
30558       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
gen/lib/Target/ARM/ARMGenInstrInfo.inc
 5456 static const MCOperandInfo OperandInfo144[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5597 static const MCOperandInfo OperandInfo285[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5597 static const MCOperandInfo OperandInfo285[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5600 static const MCOperandInfo OperandInfo288[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5600 static const MCOperandInfo OperandInfo288[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5600 static const MCOperandInfo OperandInfo288[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5615 static const MCOperandInfo OperandInfo303[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5619 static const MCOperandInfo OperandInfo307[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 5632 static const MCOperandInfo OperandInfo320[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5632 static const MCOperandInfo OperandInfo320[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5632 static const MCOperandInfo OperandInfo320[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5632 static const MCOperandInfo OperandInfo320[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5638 static const MCOperandInfo OperandInfo326[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 5638 static const MCOperandInfo OperandInfo326[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 5638 static const MCOperandInfo OperandInfo326[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 5674 static const MCOperandInfo OperandInfo362[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5687 static const MCOperandInfo OperandInfo375[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5688 static const MCOperandInfo OperandInfo376[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5709 static const MCOperandInfo OperandInfo397[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 5709 static const MCOperandInfo OperandInfo397[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 5718 static const MCOperandInfo OperandInfo406[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
 5758 static const MCOperandInfo OperandInfo446[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
gen/lib/Target/ARM/ARMGenRegisterBank.inc
   38     (1u << (ARM::HPRRegClassID - 0)) |
gen/lib/Target/ARM/ARMGenRegisterInfo.inc
 2891   { HPR, HPRBits, 1556, 32, sizeof(HPRBits), ARM::HPRRegClassID, 1, true },
 5905   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::HPRRegClassID];
 6546     &ARMMCRegisterClasses[HPRRegClassID],
lib/Target/ARM/ARMRegisterBankInfo.cpp
  196   case HPRRegClassID: