reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/ARM/ARMGenRegisterInfo.inc

 3609   extern const TargetRegisterClass GPRnopcRegClass;

References

gen/lib/Target/ARM/ARMGenFastISel.inc

 2740     return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2802     return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2883     return fastEmitInst_rr(ARM::QADD16, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2904     return fastEmitInst_rr(ARM::QADD8, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2925     return fastEmitInst_rr(ARM::QSUB16, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2946     return fastEmitInst_rr(ARM::QSUB8, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3404     return fastEmitInst_rr(ARM::t2ADDrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4154     return fastEmitInst_rr(ARM::MULv5, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4157     return fastEmitInst_rr(ARM::MUL, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4366     return fastEmitInst_rr(ARM::QADD, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4655     return fastEmitInst_rr(ARM::QSUB, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4703     return fastEmitInst_rr(ARM::t2SUBrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 6576     return fastEmitInst_ri(ARM::t2CMPri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
 6594     return fastEmitInst_ri(ARM::t2CMPri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
 6630     return fastEmitInst_ri(ARM::t2ADDri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
 6684     return fastEmitInst_ri(ARM::t2SUBri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
 6736     return fastEmitInst_ri(ARM::t2ADDri12, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
 6754     return fastEmitInst_ri(ARM::t2SUBri12, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);

gen/lib/Target/ARM/ARMGenRegisterInfo.inc

 4939   &ARM::GPRnopcRegClass,
 4965   &ARM::GPRnopcRegClass,
 4977   &ARM::GPRnopcRegClass,
 4988   &ARM::GPRnopcRegClass,
 4997   &ARM::GPRnopcRegClass,
 5010   &ARM::GPRnopcRegClass,
 5021   &ARM::GPRnopcRegClass,
 5032   &ARM::GPRnopcRegClass,
 5047   &ARM::GPRnopcRegClass,
 5061   &ARM::GPRnopcRegClass,
 5075   &ARM::GPRnopcRegClass,
 5089   &ARM::GPRnopcRegClass,
 5102   &ARM::GPRnopcRegClass,
 5117   &ARM::GPRnopcRegClass,
 5135   &ARM::GPRnopcRegClass,
 5152   &ARM::GPRnopcRegClass,
 5168   &ARM::GPRnopcRegClass,
 5190   &ARM::GPRnopcRegClass,
 8021     &ARM::GPRnopcRegClass,

lib/Target/ARM/ARMFastISel.cpp

  940       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
  955       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
  969       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
  978         RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
 1779   unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
 2623     /* ARM      */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
 2623     /* ARM      */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
 2799   unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);

lib/Target/ARM/ARMISelLowering.cpp

 9474                                                         : &ARM::GPRnopcRegClass;