|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
Declarations
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 3605 extern const TargetRegisterClass GPRRegClass;
References
gen/lib/Target/ARM/ARMGenFastISel.inc 84 return fastEmitInst_r(ARM::BLX, &ARM::GPRRegClass, Op0, Op0IsKill);
126 return fastEmitInst_r(ARM::BLX_pred, &ARM::GPRRegClass, Op0, Op0IsKill);
185 return fastEmitInst_r(ARM::RRX, &ARM::GPRRegClass, Op0, Op0IsKill);
206 return fastEmitInst_r(ARM::MOVsra_flag, &ARM::GPRRegClass, Op0, Op0IsKill);
227 return fastEmitInst_r(ARM::MOVsrl_flag, &ARM::GPRRegClass, Op0, Op0IsKill);
743 return fastEmitInst_r(ARM::VMOVRS, &ARM::GPRRegClass, Op0, Op0IsKill);
1547 return fastEmitInst_r(ARM::RBIT, &ARM::GPRRegClass, Op0, Op0IsKill);
1565 return fastEmitInst_r(ARM::tBRIND, &ARM::GPRRegClass, Op0, Op0IsKill);
1568 return fastEmitInst_r(ARM::MOVPCRX, &ARM::GPRRegClass, Op0, Op0IsKill);
1571 return fastEmitInst_r(ARM::BX, &ARM::GPRRegClass, Op0, Op0IsKill);
1595 return fastEmitInst_r(ARM::REV, &ARM::GPRRegClass, Op0, Op0IsKill);
1636 return fastEmitInst_r(ARM::CLZ, &ARM::GPRRegClass, Op0, Op0IsKill);
2746 return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2808 return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2826 return fastEmitInst_rr(ARM::tInt_WIN_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2832 return fastEmitInst_rr(ARM::Int_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2859 return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp_nofp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2862 return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2967 return fastEmitInst_rr(ARM::SMULWB, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2988 return fastEmitInst_rr(ARM::SMULWT, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3012 return fastEmitInst_rr(ARM::SUBSrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3410 return fastEmitInst_rr(ARM::ADDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3523 return fastEmitInst_rr(ARM::ANDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4247 return fastEmitInst_rr(ARM::SMMUL, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4271 return fastEmitInst_rr(ARM::ORRrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4417 return fastEmitInst_rr(ARM::SDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4709 return fastEmitInst_rr(ARM::SUBrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4857 return fastEmitInst_rr(ARM::UDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
5073 return fastEmitInst_rr(ARM::EORrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
5200 return fastEmitInst_ri(ARM::tPICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5203 return fastEmitInst_ri(ARM::PICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5292 return fastEmitInst_ri(ARM::VGETLNs8, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5310 return fastEmitInst_ri(ARM::VGETLNs16, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5340 return fastEmitInst_ri(ARM::VGETLNu8, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5358 return fastEmitInst_ri(ARM::VGETLNu16, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
6092 return fastEmitInst_ri(ARM::VGETLNi32, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
6202 return fastEmitInst_ri(ARM::CMNri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
6220 return fastEmitInst_ri(ARM::CMPri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
6238 return fastEmitInst_ri(ARM::CMPri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
6256 return fastEmitInst_ri(ARM::SUBSri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
6274 return fastEmitInst_ri(ARM::ADDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
6292 return fastEmitInst_ri(ARM::ANDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
6310 return fastEmitInst_ri(ARM::ORRri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
6328 return fastEmitInst_ri(ARM::SUBri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
6346 return fastEmitInst_ri(ARM::EORri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 4924 &ARM::GPRRegClass,
4936 &ARM::GPRRegClass,
4946 &ARM::GPRRegClass,
4957 &ARM::GPRRegClass,
4962 &ARM::GPRRegClass,
4974 &ARM::GPRRegClass,
4985 &ARM::GPRRegClass,
4994 &ARM::GPRRegClass,
5007 &ARM::GPRRegClass,
5018 &ARM::GPRRegClass,
5029 &ARM::GPRRegClass,
5044 &ARM::GPRRegClass,
5058 &ARM::GPRRegClass,
5072 &ARM::GPRRegClass,
5086 &ARM::GPRRegClass,
5099 &ARM::GPRRegClass,
5114 &ARM::GPRRegClass,
5132 &ARM::GPRRegClass,
5149 &ARM::GPRRegClass,
5165 &ARM::GPRRegClass,
5180 &ARM::GPRRegClass,
5187 &ARM::GPRRegClass,
8017 &ARM::GPRRegClass,
lib/Target/ARM/ARMBaseInstrInfo.cpp 834 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
835 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
930 assert(ARM::GPRRegClass.contains(SrcReg));
936 assert(ARM::GPRRegClass.contains(DestReg));
942 assert(ARM::GPRRegClass.contains(SrcReg));
948 assert(ARM::GPRRegClass.contains(DestReg));
1053 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1294 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
2442 RegClass = &ARM::GPRRegClass;
lib/Target/ARM/ARMBaseRegisterInfo.cpp 253 return &ARM::GPRRegClass;
lib/Target/ARM/ARMFastISel.cpp 474 &ARM::GPRRegClass;
490 &ARM::GPRRegClass;
547 : &ARM::GPRRegClass;
850 : &ARM::GPRRegClass;
1064 : &ARM::GPRRegClass);
1486 : &ARM::GPRRegClass;
1659 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1662 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
2495 : &ARM::GPRRegClass;
lib/Target/ARM/ARMFrameLowering.cpp 1713 if (!ARM::GPRRegClass.contains(Reg)) {
2118 const TargetRegisterClass &RC = ARM::GPRRegClass;
lib/Target/ARM/ARMISelLowering.cpp 689 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
2838 if (ARM::GPRRegClass.contains(*I))
3844 RC = &ARM::GPRRegClass;
3914 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
4064 : &ARM::GPRRegClass;
9360 : &ARM::GPRRegClass;
9857 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
10053 TRC = IsThumb ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
10630 isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass);
10710 : &ARM::GPRRegClass);
15684 return RCPair(0U, &ARM::GPRRegClass);
15692 return RCPair(0U, &ARM::GPRRegClass);
17108 if (ARM::GPRRegClass.contains(*I))
17109 RC = &ARM::GPRRegClass;
lib/Target/ARM/ARMInstructionSelector.cpp 207 return &ARM::GPRRegClass;
549 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
559 auto IntermediateRes = MRI.createVirtualRegister(&ARM::GPRRegClass);
688 auto AddressReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
718 auto Offset = MRI.createVirtualRegister(&ARM::GPRRegClass);
879 Register AndResult = MRI.createVirtualRegister(&ARM::GPRRegClass);
930 Register IgnoredBits = MRI.createVirtualRegister(&ARM::GPRRegClass);
1101 Register ValueToStore = MRI.createVirtualRegister(&ARM::GPRRegClass);
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 694 NewBase = findFreeReg(isThumb1 ? ARM::tGPRRegClass : ARM::GPRRegClass);
lib/Target/ARM/ARMSubtarget.cpp 462 ARM::GPRRegClass.contains(PhysReg);
lib/Target/ARM/Thumb1InstrInfo.cpp 46 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
lib/Target/ARM/Thumb2InstrInfo.cpp 126 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
148 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
190 if (ARM::GPRRegClass.hasSubClassEq(RC)) {