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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenDAGISel.inc36925 /* 81241*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
36939 /* 81273*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
36985 /* 81372*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41806 /* 91936*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41814 /* 91965*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41822 /* 91994*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41832 /* 92034*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41844 /* 92066*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41852 /* 92095*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41860 /* 92124*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41870 /* 92164*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41891 /* 92210*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41899 /* 92239*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41907 /* 92268*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41917 /* 92308*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41929 /* 92340*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41937 /* 92369*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41945 /* 92398*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41955 /* 92438*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41989 /* 92520*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
41997 /* 92549*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
42007 /* 92588*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
43064 /* 94876*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
43072 /* 94905*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
43080 /* 94934*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
43090 /* 94974*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
43102 /* 95006*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
43110 /* 95035*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
43118 /* 95064*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
43128 /* 95104*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
43160 /* 95182*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
43168 /* 95211*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
43178 /* 95250*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
43918 /* 96959*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
43928 /* 96997*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
44074 /* 97336*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
44082 /* 97365*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
44092 /* 97404*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
44583 /* 98592*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
44593 /* 98630*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
45291 /*100251*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
45299 /*100280*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
45309 /*100319*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
45321 /*100351*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
45329 /*100380*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
45339 /*100419*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
45387 /*100539*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
45395 /*100568*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
45405 /*100607*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
45417 /*100639*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
45425 /*100668*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
45435 /*100707*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
46156 /*102312*/ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5610 static const MCOperandInfo OperandInfo298[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
5613 static const MCOperandInfo OperandInfo301[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
5680 static const MCOperandInfo OperandInfo368[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5682 static const MCOperandInfo OperandInfo370[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5683 static const MCOperandInfo OperandInfo371[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5699 static const MCOperandInfo OperandInfo387[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5701 static const MCOperandInfo OperandInfo389[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5702 static const MCOperandInfo OperandInfo390[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5713 static const MCOperandInfo OperandInfo401[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
5714 static const MCOperandInfo OperandInfo402[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
gen/lib/Target/ARM/ARMGenRegisterBank.inc 47 (1u << (ARM::DPR_VFP2RegClassID - 32)) |
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 2928 { DPR_VFP2, DPR_VFP2Bits, 182, 16, sizeof(DPR_VFP2Bits), ARM::DPR_VFP2RegClassID, 1, true },
6990 &ARMMCRegisterClasses[DPR_VFP2RegClassID],
lib/Target/ARM/ARMISelDAGToDAG.cpp 1703 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, dl, MVT::i32);