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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc13269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
13994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
14012 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
14030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
14048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
14067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
14086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
15866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
16013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
16072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
16135 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
16220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
16316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
16589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
16848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
18160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
18177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
18273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
18290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_1RegClassID,
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc15446 static const MCOperandInfo OperandInfo104[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15447 static const MCOperandInfo OperandInfo105[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
15447 static const MCOperandInfo OperandInfo105[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
15488 static const MCOperandInfo OperandInfo146[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15488 static const MCOperandInfo OperandInfo146[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15489 static const MCOperandInfo OperandInfo147[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
15490 static const MCOperandInfo OperandInfo148[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
15490 static const MCOperandInfo OperandInfo148[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
15491 static const MCOperandInfo OperandInfo149[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
15491 static const MCOperandInfo OperandInfo149[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
15491 static const MCOperandInfo OperandInfo149[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
15506 static const MCOperandInfo OperandInfo164[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
15538 static const MCOperandInfo OperandInfo196[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
15621 static const MCOperandInfo OperandInfo279[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::SReg_1_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15632 static const MCOperandInfo OperandInfo290[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15653 static const MCOperandInfo OperandInfo311[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15656 static const MCOperandInfo OperandInfo314[] = { { AMDGPU::SReg_1RegClassID, 0, AMDGPU::OPERAND_SDWA_VOPC_DST, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15658 static const MCOperandInfo OperandInfo316[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15661 static const MCOperandInfo OperandInfo319[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP16, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
15664 static const MCOperandInfo OperandInfo322[] = { { AMDGPU::SReg_1RegClassID, 0, AMDGPU::OPERAND_SDWA_VOPC_DST, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15665 static const MCOperandInfo OperandInfo323[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
15668 static const MCOperandInfo OperandInfo326[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
15670 static const MCOperandInfo OperandInfo328[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15673 static const MCOperandInfo OperandInfo331[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT16, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT16, 0 }, };
15676 static const MCOperandInfo OperandInfo334[] = { { AMDGPU::SReg_1RegClassID, 0, AMDGPU::OPERAND_SDWA_VOPC_DST, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15678 static const MCOperandInfo OperandInfo336[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
15681 static const MCOperandInfo OperandInfo339[] = { { AMDGPU::SReg_1RegClassID, 0, AMDGPU::OPERAND_SDWA_VOPC_DST, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15683 static const MCOperandInfo OperandInfo341[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
15706 static const MCOperandInfo OperandInfo364[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, };
15707 static const MCOperandInfo OperandInfo365[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, };
15743 static const MCOperandInfo OperandInfo401[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
gen/lib/Target/AMDGPU/AMDGPUGenRegisterBank.inc 68 (1u << (AMDGPU::SReg_1RegClassID - 0)) |
162 (1u << (AMDGPU::SReg_1RegClassID - 0)) |
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc11244 { SReg_1, SReg_1Bits, 96, 209, sizeof(SReg_1Bits), AMDGPU::SReg_1RegClassID, 1, false },
20348 &AMDGPUMCRegisterClasses[SReg_1RegClassID],
lib/Target/AMDGPU/SIRegisterInfo.cpp 1851 case AMDGPU::SReg_1RegClassID: