reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
17352 extern const TargetRegisterClass SGPR_64RegClass;
19792 &AMDGPU::SGPR_64RegClass, 21737 &AMDGPU::SGPR_64RegClass,lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp
91 &AMDGPU::SGPR_64RegClass); 108 &AMDGPU::SGPR_64RegClass); 111 &AMDGPU::SGPR_64RegClass); 114 &AMDGPU::SGPR_64RegClass); 117 &AMDGPU::SGPR_64RegClass); 120 &AMDGPU::SGPR_64RegClass); 123 &AMDGPU::SGPR_64RegClass);lib/Target/AMDGPU/AMDGPUCallLowering.cpp
330 &AMDGPU::SGPR_64RegClass); 400 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass); 406 MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass); 423 MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass); 429 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass); 579 &AMDGPU::SGPR_64RegClass); 586 MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);lib/Target/AMDGPU/SIISelLowering.cpp
1696 return allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_64RegClass, 16); 1763 MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass); 1776 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass); 1782 MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass); 1791 Register VReg = MF.addLiveIn(InputPtrReg, &AMDGPU::SGPR_64RegClass); 1797 MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass); 1803 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass); 1997 RC = &AMDGPU::SGPR_64RegClass; 10558 RC = &AMDGPU::SGPR_64RegClass;lib/Target/AMDGPU/SIInstrInfo.cpp
767 RegClass == &AMDGPU::SGPR_64RegClass || 2222 EltRC = &AMDGPU::SGPR_64RegClass;