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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc14791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_512RegClassID,
14847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_512RegClassID,
14903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_512RegClassID,
14959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_512RegClassID,
15043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_512RegClassID,
15099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_512RegClassID,
15155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_512RegClassID,
15211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_512RegClassID,
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc15514 static const MCOperandInfo OperandInfo172[] = { { AMDGPU::AReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15515 static const MCOperandInfo OperandInfo173[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AMDGPU::AReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15745 static const MCOperandInfo OperandInfo403[] = { { AMDGPU::AReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_512RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15745 static const MCOperandInfo OperandInfo403[] = { { AMDGPU::AReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_512RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15746 static const MCOperandInfo OperandInfo404[] = { { AMDGPU::AReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_512RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15746 static const MCOperandInfo OperandInfo404[] = { { AMDGPU::AReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_512RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15747 static const MCOperandInfo OperandInfo405[] = { { AMDGPU::AReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_512RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15747 static const MCOperandInfo OperandInfo405[] = { { AMDGPU::AReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_512RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc11317 { AReg_512, AReg_512Bits, 151, 241, sizeof(AReg_512Bits), AMDGPU::AReg_512RegClassID, 33, true },
21224 &AMDGPUMCRegisterClasses[AReg_512RegClassID],
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 585 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i32);
589 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i16);
597 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f32);
601 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f16);
1931 case 16: return AMDGPU::AReg_512RegClassID;
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp 715 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);
944 case OPW512: return AReg_512RegClassID;
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp 1117 case AMDGPU::AReg_512RegClassID: