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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc14679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_128RegClassID,
14707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_128RegClassID,
14735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_128RegClassID,
14763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_128RegClassID,
14819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_128RegClassID,
14875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_128RegClassID,
14931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_128RegClassID,
14987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_128RegClassID,
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc15510 static const MCOperandInfo OperandInfo168[] = { { AMDGPU::AReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15511 static const MCOperandInfo OperandInfo169[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AMDGPU::AReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15744 static const MCOperandInfo OperandInfo402[] = { { AMDGPU::AReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_128RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15744 static const MCOperandInfo OperandInfo402[] = { { AMDGPU::AReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_128RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15748 static const MCOperandInfo OperandInfo406[] = { { AMDGPU::AReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_128RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15748 static const MCOperandInfo OperandInfo406[] = { { AMDGPU::AReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_128RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15749 static const MCOperandInfo OperandInfo407[] = { { AMDGPU::AReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_128RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15749 static const MCOperandInfo OperandInfo407[] = { { AMDGPU::AReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_128RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc11283 { AReg_128, AReg_128Bits, 3238, 253, sizeof(AReg_128Bits), AMDGPU::AReg_128RegClassID, 9, true },
20816 &AMDGPUMCRegisterClasses[AReg_128RegClassID],
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 561 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i32);
565 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i16);
573 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f32);
577 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f16);
1930 case 4: return AMDGPU::AReg_128RegClassID;
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp 711 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);
943 case OPW128: return AReg_128RegClassID;
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp 1106 case AMDGPU::AReg_128RegClassID: