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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc15015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_1024RegClassID,
15071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_1024RegClassID,
15127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_1024RegClassID,
15183 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::AReg_1024RegClassID,
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc15508 static const MCOperandInfo OperandInfo166[] = { { AMDGPU::AReg_1024RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15509 static const MCOperandInfo OperandInfo167[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AMDGPU::AReg_1024RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15750 static const MCOperandInfo OperandInfo408[] = { { AMDGPU::AReg_1024RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_1024RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15750 static const MCOperandInfo OperandInfo408[] = { { AMDGPU::AReg_1024RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_1024RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15751 static const MCOperandInfo OperandInfo409[] = { { AMDGPU::AReg_1024RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_1024RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15751 static const MCOperandInfo OperandInfo409[] = { { AMDGPU::AReg_1024RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_1024RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15752 static const MCOperandInfo OperandInfo410[] = { { AMDGPU::AReg_1024RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_1024RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15752 static const MCOperandInfo OperandInfo410[] = { { AMDGPU::AReg_1024RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_1024RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc11335 { AReg_1024, AReg_1024Bits, 648, 225, sizeof(AReg_1024Bits), AMDGPU::AReg_1024RegClassID, 65, true },
21440 &AMDGPUMCRegisterClasses[AReg_1024RegClassID],
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 609 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i32);
613 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i16);
621 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f32);
625 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f16);
1932 case 32: return AMDGPU::AReg_1024RegClassID;
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp 719 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);
945 case OPW1024: return AReg_1024RegClassID;
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp 1121 case AMDGPU::AReg_1024RegClassID: