|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenRegisterBank.inc 224 &AMDGPU::VGPRRegBank,
lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def 52 {0, 1, VGPRRegBank}, // VGPR begin
53 {0, 16, VGPRRegBank},
54 {0, 32, VGPRRegBank},
55 {0, 64, VGPRRegBank},
56 {0, 128, VGPRRegBank},
57 {0, 256, VGPRRegBank},
58 {0, 512, VGPRRegBank},
59 {0, 1024, VGPRRegBank},
61 {0, 96, VGPRRegBank}
106 {0, 32, VGPRRegBank}, // 32-bit op
107 {0, 32, VGPRRegBank}, // 2x32-bit op
108 {32, 32, VGPRRegBank},
173 /* 8 32-bit loads */ {0, 32, VGPRRegBank}, {32, 32, VGPRRegBank},
173 /* 8 32-bit loads */ {0, 32, VGPRRegBank}, {32, 32, VGPRRegBank},
174 {64, 32, VGPRRegBank}, {96, 32, VGPRRegBank},
174 {64, 32, VGPRRegBank}, {96, 32, VGPRRegBank},
175 {128, 32, VGPRRegBank}, {160, 32, VGPRRegBank},
175 {128, 32, VGPRRegBank}, {160, 32, VGPRRegBank},
176 {192, 32, VGPRRegBank}, {224, 32, VGPRRegBank},
176 {192, 32, VGPRRegBank}, {224, 32, VGPRRegBank},
177 /* 16 32-bit loads */ {0, 32, VGPRRegBank}, {32, 32, VGPRRegBank},
177 /* 16 32-bit loads */ {0, 32, VGPRRegBank}, {32, 32, VGPRRegBank},
178 {64, 32, VGPRRegBank}, {96, 32, VGPRRegBank},
178 {64, 32, VGPRRegBank}, {96, 32, VGPRRegBank},
179 {128, 32, VGPRRegBank}, {160, 32, VGPRRegBank},
179 {128, 32, VGPRRegBank}, {160, 32, VGPRRegBank},
180 {192, 32, VGPRRegBank}, {224, 32, VGPRRegBank},
180 {192, 32, VGPRRegBank}, {224, 32, VGPRRegBank},
181 {256, 32, VGPRRegBank}, {288, 32, VGPRRegBank},
181 {256, 32, VGPRRegBank}, {288, 32, VGPRRegBank},
182 {320, 32, VGPRRegBank}, {352, 32, VGPRRegBank},
182 {320, 32, VGPRRegBank}, {352, 32, VGPRRegBank},
183 {384, 32, VGPRRegBank}, {416, 32, VGPRRegBank},
183 {384, 32, VGPRRegBank}, {416, 32, VGPRRegBank},
184 {448, 32, VGPRRegBank}, {480, 32, VGPRRegBank},
184 {448, 32, VGPRRegBank}, {480, 32, VGPRRegBank},
185 /* 4 64-bit loads */ {0, 64, VGPRRegBank}, {64, 64, VGPRRegBank},
185 /* 4 64-bit loads */ {0, 64, VGPRRegBank}, {64, 64, VGPRRegBank},
186 {128, 64, VGPRRegBank}, {192, 64, VGPRRegBank},
186 {128, 64, VGPRRegBank}, {192, 64, VGPRRegBank},
187 /* 8 64-bit loads */ {0, 64, VGPRRegBank}, {64, 64, VGPRRegBank},
187 /* 8 64-bit loads */ {0, 64, VGPRRegBank}, {64, 64, VGPRRegBank},
188 {128, 64, VGPRRegBank}, {192, 64, VGPRRegBank},
188 {128, 64, VGPRRegBank}, {192, 64, VGPRRegBank},
189 {256, 64, VGPRRegBank}, {320, 64, VGPRRegBank},
189 {256, 64, VGPRRegBank}, {320, 64, VGPRRegBank},
190 {384, 64, VGPRRegBank}, {448, 64, VGPRRegBank},
190 {384, 64, VGPRRegBank}, {448, 64, VGPRRegBank},
199 /* 2 128-bit loads */ {0, 128, VGPRRegBank}, {128, 128, VGPRRegBank},
199 /* 2 128-bit loads */ {0, 128, VGPRRegBank}, {128, 128, VGPRRegBank},
200 /* 4 128-bit loads */ {0, 128, VGPRRegBank}, {128, 128, VGPRRegBank},
200 /* 4 128-bit loads */ {0, 128, VGPRRegBank}, {128, 128, VGPRRegBank},
201 {256, 128, VGPRRegBank}, {384, 128, VGPRRegBank}
201 {256, 128, VGPRRegBank}, {384, 128, VGPRRegBank}
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 107 assert(&RBVGPR == &AMDGPU::VGPRRegBank);
172 return TRI->isSGPRClass(&RC) ? AMDGPU::SGPRRegBank : AMDGPU::VGPRRegBank;
1003 if (Bank != &AMDGPU::VGPRRegBank)
1078 ApplyRegBankMapping O(MRI, &AMDGPU::VGPRRegBank);
1443 if (DstBank == &AMDGPU::VGPRRegBank)
1464 if (DstBank == &AMDGPU::VGPRRegBank)
1541 &AMDGPU::SGPRRegBank : &AMDGPU::VGPRRegBank;