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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenRegisterBank.inc 215 RegisterBank SGPRRegBank(/* ID */ AMDGPU::SGPRRegBankID, /* Name */ "SGPR", /* Size */ 1024, /* CoveredRegClasses */ SGPRRegBankCoverageData, /* NumRegClasses */ 114);
lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def 139 Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1;
143 Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96;
166 assert(BankID == AMDGPU::SGPRRegBankID);
216 if (Size < 256 || BankID == AMDGPU::SGPRRegBankID)
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 290 if (DstRB->getID() == AMDGPU::SGPRRegBankID) {
306 const bool IsSALU = DstRB->getID() == AMDGPU::SGPRRegBankID;
1301 if (SrcBank->getID() == AMDGPU::SGPRRegBankID && DstSize <= 64) {
1415 IsSgpr = RB->getID() == AMDGPU::SGPRRegBankID;
1498 if (OpBank->getID() == AMDGPU::SGPRRegBankID)
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 101 const RegisterBank &RBSGPR = getRegBank(AMDGPU::SGPRRegBankID);
115 if (Dst.getID() == AMDGPU::SGPRRegBankID &&
129 Dst.getID() == AMDGPU::SGPRRegBankID) &&
130 (Src.getID() == AMDGPU::SGPRRegBankID ||
220 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 },
220 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 },
223 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 2 }
232 { { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 },
232 { { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 },
235 { { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, 2 },
238 { { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 2 },
261 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 },
261 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 },
262 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 },
266 { { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1000 },
277 { { AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 },
277 { { AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 },
280 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, 300 },
283 { { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1000 },
298 { { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 },
312 { { AMDGPU::SGPRRegBankID }, 1 },
352 { { AMDGPU::SGPRRegBankID }, 1 },
367 { { AMDGPU::SGPRRegBankID }, 1 }
382 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
383 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
389 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
390 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
391 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
410 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
411 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
412 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
427 AMDGPU::getValueMappingSGPR64Only(AMDGPU::SGPRRegBankID, Size),
438 AMDGPU::getValueMappingSGPR64Only(AMDGPU::SGPRRegBankID, Size)}),
456 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
457 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, PtrSize)}),
483 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
484 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
491 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
500 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
517 getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
519 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
520 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
540 { { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 },
541 { { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 },
545 { { AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID }, 3 }
545 { { AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID }, 3 }
545 { { AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID }, 3 }
558 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
560 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
561 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
913 MRI.setRegBank(Op.getReg(), getRegBank(AMDGPU::SGPRRegBankID));
1914 assert(Bank->getID() == AMDGPU::SGPRRegBankID ||
1929 unsigned BankID = Size == 1 ? AMDGPU::SCCRegBankID : AMDGPU::SGPRRegBankID;
2019 unsigned NewBank = getRegBankID(OpReg, MRI, *TRI, AMDGPU::SGPRRegBankID);
2053 ValMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
2054 PtrMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, PtrSize);
2082 return (RB0 == AMDGPU::SGPRRegBankID && RB1 == AMDGPU::SGPRRegBankID) ?
2082 return (RB0 == AMDGPU::SGPRRegBankID && RB1 == AMDGPU::SGPRRegBankID) ?
2083 AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
2092 unsigned Bank = getRegBankID(Reg, MRI, TRI, AMDGPU::SGPRRegBankID);
2119 unsigned BankID = AMDGPU::SGPRRegBankID;
2125 if (OpBank != AMDGPU::SGPRRegBankID) {
2160 OpBank = AMDGPU::SGPRRegBankID;
2213 BankLHS = AMDGPU::SGPRRegBankID;
2214 BankRHS = AMDGPU::SGPRRegBankID;
2217 AMDGPU::SGPRRegBankID);
2219 AMDGPU::SGPRRegBankID);
2234 } else if (BankLHS == AMDGPU::SGPRRegBankID && BankRHS == AMDGPU::SGPRRegBankID) {
2234 } else if (BankLHS == AMDGPU::SGPRRegBankID && BankRHS == AMDGPU::SGPRRegBankID) {
2235 TargetBankID = AMDGPU::SGPRRegBankID;
2241 BankLHS = AMDGPU::SGPRRegBankID;
2242 BankRHS = AMDGPU::SGPRRegBankID;
2255 OpdsMapping[0] = getValueMappingSGPR64Only(AMDGPU::SGPRRegBankID, Size);
2326 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
2334 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
2345 unsigned BankID = isSALUMapping(MI) ? AMDGPU::SGPRRegBankID :
2386 AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
2436 case AMDGPU::SGPRRegBankID:
2437 DstBank = AMDGPU::SGPRRegBankID;
2490 bool CanUseSCC = Op2Bank == AMDGPU::SGPRRegBankID &&
2491 Op3Bank == AMDGPU::SGPRRegBankID &&
2522 AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
2542 unsigned Bank = isSALUMapping(MI) ? AMDGPU::SGPRRegBankID :
2619 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
2640 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size0);
2681 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, DstSize);
2693 unsigned IdxBank = getRegBankID(IdxReg, MRI, *TRI, AMDGPU::SGPRRegBankID);
2700 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, DstSize);
2708 unsigned SrcBank = getRegBankID(SrcReg, MRI, *TRI, AMDGPU::SGPRRegBankID);
2711 unsigned IdxBank = getRegBankID(IdxReg, MRI, *TRI, AMDGPU::SGPRRegBankID);
2723 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
2725 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
2739 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
2755 AMDGPU::SGPRRegBankID);
2763 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
2764 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
2769 OpdsMapping[5] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
2770 OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
2808 AMDGPU::SGPRRegBankID);
2815 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
2821 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, WaveSize);
2822 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, WaveSize);
2868 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
2869 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
2879 AMDGPU::SGPRRegBankID);
2888 AMDGPU::SGPRRegBankID);
2909 AMDGPU::SGPRRegBankID);
2911 AMDGPU::SGPRRegBankID);
2912 bool SGPRSrcs = Op2Bank == AMDGPU::SGPRRegBankID &&
2913 Op3Bank == AMDGPU::SGPRRegBankID;
2919 if (CondBank == AMDGPU::SGPRRegBankID)
2925 AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
2966 AMDGPU::SGPRRegBankID);
lib/Target/AMDGPU/SIRegisterInfo.cpp 1787 case AMDGPU::SGPRRegBankID: