reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenRegisterBank.inc

  222     &AMDGPU::SGPRRegBank,

lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def

   43   {0, 1,  SGPRRegBank}, // SGPR begin
   44   {0, 16, SGPRRegBank},
   45   {0, 32, SGPRRegBank},
   46   {0, 64, SGPRRegBank},
   47   {0, 128, SGPRRegBank},
   48   {0, 256, SGPRRegBank},
   49   {0, 512, SGPRRegBank},
   50   {0, 1024, SGPRRegBank},
   60   {0, 96, SGPRRegBank},
  101   {0, 32, SGPRRegBank}, // 32-bit op
  102   {0, 32, SGPRRegBank}, // 2x32-bit op
  103   {32, 32, SGPRRegBank},
  104   {0, 64, SGPRRegBank}, // <2x32-bit> op
  171   /* 256-bit load */    {0, 256, SGPRRegBank},
  172   /* 512-bit load */    {0, 512, SGPRRegBank},

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

   69         RB = (NewBank == &AMDGPU::SGPRRegBank ?
  103   assert(&RBSGPR == &AMDGPU::SGPRRegBank);
  172   return TRI->isSGPRClass(&RC) ? AMDGPU::SGPRRegBank : AMDGPU::VGPRRegBank;
 1055     if (PtrBank == &AMDGPU::SGPRRegBank)
 1449     ApplyRegBankMapping ApplySALU(MRI, &AMDGPU::SGPRRegBank);
 1469     ApplyRegBankMapping ApplySALU(MRI, &AMDGPU::SGPRRegBank);
 1505         SrcBank != &AMDGPU::SGPRRegBank &&
 1541         &AMDGPU::SGPRRegBank : &AMDGPU::VGPRRegBank;
 1603     if (DstBank == &AMDGPU::SGPRRegBank)
 1697     MRI.setRegBank(One.getReg(0), AMDGPU::SGPRRegBank);
 1698     MRI.setRegBank(IdxLo.getReg(0), AMDGPU::SGPRRegBank);
 1699     MRI.setRegBank(IdxHi.getReg(0), AMDGPU::SGPRRegBank);
 1767     MRI.setRegBank(One.getReg(0), AMDGPU::SGPRRegBank);
 1768     MRI.setRegBank(IdxLo.getReg(0), AMDGPU::SGPRRegBank);
 1769     MRI.setRegBank(IdxHi.getReg(0), AMDGPU::SGPRRegBank);
 2048   if (PtrBank == &AMDGPU::SGPRRegBank &&