reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc

21333   { 25672 /* v_readfirstlane_b32 */, AMDGPU::V_READFIRSTLANE_B32, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_SReg_32, MCK_VRegOrLds_32 }, },

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

34138 /* 72482*/        OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::V_READFIRSTLANE_B32), 0,

gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc

13302         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_READFIRSTLANE_B32,

gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc

55503   case AMDGPU::V_READFIRSTLANE_B32:

gen/lib/Target/AMDGPU/AMDGPUGenMCCodeEmitter.inc

33606     case AMDGPU::V_READFIRSTLANE_B32:

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

 2295       = CurDAG->getMachineNode(AMDGPU::V_READFIRSTLANE_B32, SL, MVT::i32,

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

  782           BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
  844               BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
  849               BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
  875               BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
 1008   B.buildInstr(AMDGPU::V_READFIRSTLANE_B32)

lib/Target/AMDGPU/GCNHazardRecognizer.cpp

  956   case AMDGPU::V_READFIRSTLANE_B32:

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

  626                     TII->get(AMDGPU::V_READFIRSTLANE_B32), TmpReg)

lib/Target/AMDGPU/SIFoldOperands.cpp

  773     if (UseOpc == AMDGPU::V_READFIRSTLANE_B32 ||

lib/Target/AMDGPU/SIISelLowering.cpp

 3202   BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentIdxReg)

lib/Target/AMDGPU/SIInstrInfo.cpp

 2779   if (Opcode == AMDGPU::V_READFIRSTLANE_B32 || Opcode == AMDGPU::V_READLANE_B32)
 4038       BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
 4045       BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
 4071     BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
 4142       BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
 4148       BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
 4229             get(AMDGPU::V_READFIRSTLANE_B32), DstReg)
 4238             get(AMDGPU::V_READFIRSTLANE_B32), SGPR)
 4350   BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub0)
 4352   BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub1)
 4354   BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub2)
 4356   BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub3)

lib/Target/AMDGPU/SIRegisterInfo.cpp

  935         BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg)