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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc59767 /*130714*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
59827 /*130827*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
59853 /*130891*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
59879 /*130955*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
59905 /*131019*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
59931 /*131083*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
59957 /*131147*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
59983 /*131211*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
60010 /*131277*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
60037 /*131343*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
60064 /*131409*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
62440 /*136562*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
63195 /*137960*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
63315 /*138205*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
74881 /*165824*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
74937 /*165981*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
75055 /*166257*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
75070 /*166285*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
75136 /*166450*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc17910 GIR_BuildMI, /*InsnID*/4, /*Opcode*/AMDGPU::V_MOV_B32_e32,
17947 GIR_BuildMI, /*InsnID*/4, /*Opcode*/AMDGPU::V_MOV_B32_e32,
18746 GIR_BuildMI, /*InsnID*/4, /*Opcode*/AMDGPU::V_MOV_B32_e32,
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc55262 case AMDGPU::V_MOV_B32_e32:
92784 { AMDGPU::V_MOV_B32_sdwa, AMDGPU::V_MOV_B32_e32 },
93410 { AMDGPU::V_MOV_B32_e32, AMDGPU::V_MOV_B32_dpp },
97140 { AMDGPU::V_MOV_B32_e32, AMDGPU::V_MOV_B32_e32_gfx6_gfx7, AMDGPU::V_MOV_B32_e32_vi, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, AMDGPU::V_MOV_B32_e32_gfx10, (uint16_t)-1U },
97859 { AMDGPU::V_MOV_B32_e32, AMDGPU::V_MOV_B32_sdwa },
98795 { AMDGPU::V_MOV_B32_e64, AMDGPU::V_MOV_B32_e32 },
99378 { AMDGPU::V_MOV_B32_e32, AMDGPU::V_MOV_B32_e64 },
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 1225 MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
1303 = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
1494 MachineSDNode *MovHighBits = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 955 B.buildInstr(AMDGPU::V_MOV_B32_e32)
960 B.buildInstr(AMDGPU::V_MOV_B32_e32)
1426 unsigned Opcode = IsSgpr ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
1604 I.setDesc(TII.get(IsVGPR ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32));
1625 unsigned MovOpc = IsVGPR ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
2013 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::V_MOV_B32_e32),
lib/Target/AMDGPU/GCNDPPCombine.cpp 144 case AMDGPU::V_MOV_B32_e32: {
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 897 TII->get(AMDGPU::V_MOV_B32_e32))
lib/Target/AMDGPU/SIAddIMGInit.cpp 144 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), PrevDst)
155 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), SubReg)
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 345 case AMDGPU::V_MOV_B32_e32:
lib/Target/AMDGPU/SIFoldOperands.cpp 922 return IsScalar ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
996 MI->setDesc(TII->get(UseCopy ? AMDGPU::COPY : AMDGPU::V_MOV_B32_e32));
lib/Target/AMDGPU/SIFrameLowering.cpp 123 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg)
170 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg)
lib/Target/AMDGPU/SIISelLowering.cpp 3417 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3446 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
lib/Target/AMDGPU/SIInstrInfo.cpp 134 case AMDGPU::V_MOV_B32_e32:
535 AMDGPU::V_ACCVGPR_READ_B32 : AMDGPU::V_MOV_B32_e32;
682 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
775 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
786 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
971 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
1428 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1431 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1436 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1439 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1455 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
2254 case AMDGPU::V_MOV_B32_e32:
2319 case AMDGPU::V_MOV_B32_e32:
2334 unsigned NewOpc = isVGPRCopy ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
2599 if (Def && Def->getOpcode() == AMDGPU::V_MOV_B32_e32 &&
3741 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
3834 unsigned Opcode = (Size == 64) ? AMDGPU::V_MOV_B64_PSEUDO : AMDGPU::V_MOV_B32_e32;
5668 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5683 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5697 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
6428 case AMDGPU::V_MOV_B32_e32: {
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 1194 TII->get(AMDGPU::V_MOV_B32_e32), VGPR);
lib/Target/AMDGPU/SIRegisterInfo.cpp 356 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), BaseReg)
368 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), FIReg)
824 = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR)
1105 bool IsCopy = MI->getOpcode() == AMDGPU::V_MOV_B32_e32;
1230 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
lib/Target/AMDGPU/SIShrinkInstructions.cpp 457 assert(MovT.getOpcode() == AMDGPU::V_MOV_B32_e32 ||
480 if ((MovY.getOpcode() != AMDGPU::V_MOV_B32_e32 &&
509 (I->getOpcode() != AMDGPU::V_MOV_B32_e32 &&
569 if (MI.getOpcode() == AMDGPU::V_MOV_B32_e32) {
590 if (ST.hasSwap() && (MI.getOpcode() == AMDGPU::V_MOV_B32_e32 ||