reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

54583 /*119639*/            OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_OR_B32), 0,
54641 /*119787*/            OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_OR_B32), 0,
74850 /*165736*/        OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_OR_B32), 0,
74859 /*165761*/          OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_OR_B32), 0,
74962 /*166050*/        OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_OR_B32), 0,
74974 /*166082*/          OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_OR_B32), 0,

gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc

 1412         GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_OR_B32,
17761         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_OR_B32,
17847         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_OR_B32,
17996         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_OR_B32,

gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc

58908   case AMDGPU::S_OR_B32:
95484   { AMDGPU::S_OR_B32, AMDGPU::S_OR_B32_gfx6_gfx7, AMDGPU::S_OR_B32_vi, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, AMDGPU::S_OR_B32_gfx10, (uint16_t)-1U },

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

  254     return Is64 ? AMDGPU::S_OR_B64 : AMDGPU::S_OR_B32;

lib/Target/AMDGPU/SIFoldOperands.cpp

  880   case AMDGPU::S_OR_B32:
 1031       Opc == AMDGPU::S_OR_B32) {
 1039       mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_OR_B32)));

lib/Target/AMDGPU/SIISelLowering.cpp

10511     PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,

lib/Target/AMDGPU/SIInstrInfo.cpp

 1403     MI.setDesc(get(AMDGPU::S_OR_B32));
 3760   case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e64;
 4852       splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32, MDT);
 4983       splitScalarNotBinop(Worklist, Inst, AMDGPU::S_OR_B32);
 4993       splitScalarBinOpN2(Worklist, Inst, AMDGPU::S_OR_B32);

lib/Target/AMDGPU/SILowerControlFlow.cpp

  506     OrOpc = AMDGPU::S_OR_B32;
  560       case AMDGPU::S_OR_B32:

lib/Target/AMDGPU/SILowerI1Copies.cpp

  467     OrOp = AMDGPU::S_OR_B32;

lib/Target/AMDGPU/SIOptimizeExecMasking.cpp

  118   case AMDGPU::S_OR_B32:
  158   case AMDGPU::S_OR_B32:
  202     MI.setDesc(TII.get(AMDGPU::S_OR_B32));

lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

   88     return MI.getOpcode() == AMDGPU::S_OR_B32 &&

lib/Target/AMDGPU/SIShrinkInstructions.cpp

  339     } else if (Opc == AMDGPU::S_OR_B32) {
  687           MI.getOpcode() == AMDGPU::S_OR_B32 ||