|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc52790 /*114577*/ OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_ANDN2_B64), 0,
52810 /*114625*/ OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_ANDN2_B64), 0,
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc58873 case AMDGPU::S_ANDN2_B64:
95133 { AMDGPU::S_ANDN2_B64, AMDGPU::S_ANDN2_B64_gfx6_gfx7, AMDGPU::S_ANDN2_B64_vi, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, AMDGPU::S_ANDN2_B64_gfx10, (uint16_t)-1U },
lib/Target/AMDGPU/SIInsertSkips.cpp 293 unsigned Opcode = KillVal ? AMDGPU::S_ANDN2_B64 : AMDGPU::S_AND_B64;
lib/Target/AMDGPU/SIInstrInfo.cpp 1409 MI.setDesc(get(AMDGPU::S_ANDN2_B64));
4879 case AMDGPU::S_ANDN2_B64:
lib/Target/AMDGPU/SILowerI1Copies.cpp 477 AndN2Op = AMDGPU::S_ANDN2_B64;
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 104 case AMDGPU::S_ANDN2_B64:
146 case AMDGPU::S_ANDN2_B64:
208 MI.setDesc(TII.get(AMDGPU::S_ANDN2_B64));
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 196 const unsigned Andn2Opc = Wave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64;