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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc52785 /*114566*/ OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_ANDN2_B32), 0,
52805 /*114614*/ OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_ANDN2_B32), 0,
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc58871 case AMDGPU::S_ANDN2_B32:
95132 { AMDGPU::S_ANDN2_B32, AMDGPU::S_ANDN2_B32_gfx6_gfx7, AMDGPU::S_ANDN2_B32_vi, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, AMDGPU::S_ANDN2_B32_gfx10, (uint16_t)-1U },
lib/Target/AMDGPU/SIInsertSkips.cpp 295 Opcode = KillVal ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_AND_B32;
lib/Target/AMDGPU/SIInstrInfo.cpp 1415 MI.setDesc(get(AMDGPU::S_ANDN2_B32));
4880 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_ANDN2_B32, MDT);
4987 case AMDGPU::S_ANDN2_B32:
lib/Target/AMDGPU/SILowerI1Copies.cpp 469 AndN2Op = AMDGPU::S_ANDN2_B32;
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 120 case AMDGPU::S_ANDN2_B32:
162 case AMDGPU::S_ANDN2_B32:
214 MI.setDesc(TII.get(AMDGPU::S_ANDN2_B32));
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 196 const unsigned Andn2Opc = Wave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64;
lib/Target/AMDGPU/SIShrinkInstructions.cpp 337 Opc = AMDGPU::S_ANDN2_B32;
356 if ((Opc == AMDGPU::S_ANDN2_B32 || Opc == AMDGPU::S_ORN2_B32) &&