|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc31989 /* 67665*/ OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
32163 /* 68092*/ OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
32212 /* 68216*/ OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
32228 /* 68257*/ OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
32244 /* 68298*/ OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
35524 /* 75292*/ OPC_MorphNodeTo0, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc 8337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
8467 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
8684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
8814 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
9332 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
9355 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
9978 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
10001 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_STORE_DWORD_OFFSET,
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc50556 case AMDGPU::BUFFER_STORE_DWORD_OFFSET:
91716 { AMDGPU::BUFFER_STORE_DWORD_OFFSET, AMDGPU::BUFFER_STORE_DWORD_ADDR64 },
94429 { AMDGPU::BUFFER_STORE_DWORD_OFFSET, AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx6_gfx7, AMDGPU::BUFFER_STORE_DWORD_OFFSET_vi, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx10, (uint16_t)-1U },
gen/lib/Target/AMDGPU/AMDGPUGenSearchableTables.inc10583 { BUFFER_STORE_DWORDX2_OFFSET, BUFFER_STORE_DWORD_OFFSET, 0x2, 0x0, 0x1, 0x1 }, // 681
10592 { BUFFER_STORE_DWORDX3_OFFSET, BUFFER_STORE_DWORD_OFFSET, 0x3, 0x0, 0x1, 0x1 }, // 690
10601 { BUFFER_STORE_DWORDX4_OFFSET, BUFFER_STORE_DWORD_OFFSET, 0x4, 0x0, 0x1, 0x1 }, // 699
10610 { BUFFER_STORE_DWORD_OFFSET, BUFFER_STORE_DWORD_OFFSET, 0x1, 0x0, 0x1, 0x1 }, // 708
10610 { BUFFER_STORE_DWORD_OFFSET, BUFFER_STORE_DWORD_OFFSET, 0x1, 0x0, 0x1, 0x1 }, // 708
11483 { BUFFER_STORE_DWORD_OFFSET, 0x1, 708 },
11484 { BUFFER_STORE_DWORD_OFFSET, 0x2, 681 },
11485 { BUFFER_STORE_DWORD_OFFSET, 0x3, 690 },
11486 { BUFFER_STORE_DWORD_OFFSET, 0x4, 699 },
12372 { BUFFER_STORE_DWORD_OFFSET, 708 },
lib/Target/AMDGPU/SIFrameLowering.cpp 106 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::BUFFER_STORE_DWORD_OFFSET))
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 315 case AMDGPU::BUFFER_STORE_DWORD_OFFSET:
lib/Target/AMDGPU/SIRegisterInfo.cpp 492 return AMDGPU::BUFFER_STORE_DWORD_OFFSET;
1046 buildSpillLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET,