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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc29163 /* 61283*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
29400 /* 61904*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
35354 /* 74899*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
39860 /* 85585*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
39975 /* 85838*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
40090 /* 86094*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
40421 /* 87012*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc 4278 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4326 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4350 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4374 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
4446 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc50510 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET:
91682 { AMDGPU::BUFFER_LOAD_DWORD_OFFSET, AMDGPU::BUFFER_LOAD_DWORD_ADDR64 },
94139 { AMDGPU::BUFFER_LOAD_DWORD_OFFSET, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx6_gfx7, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_vi, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx10, (uint16_t)-1U },
gen/lib/Target/AMDGPU/AMDGPUGenSearchableTables.inc10250 { BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORD_OFFSET, 0x2, 0x0, 0x1, 0x1 }, // 348
10268 { BUFFER_LOAD_DWORDX3_OFFSET, BUFFER_LOAD_DWORD_OFFSET, 0x3, 0x0, 0x1, 0x1 }, // 366
10286 { BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORD_OFFSET, 0x4, 0x0, 0x1, 0x1 }, // 384
10304 { BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFSET, 0x1, 0x0, 0x1, 0x1 }, // 402
10304 { BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFSET, 0x1, 0x0, 0x1, 0x1 }, // 402
11177 { BUFFER_LOAD_DWORD_OFFSET, 0x1, 402 },
11178 { BUFFER_LOAD_DWORD_OFFSET, 0x2, 348 },
11179 { BUFFER_LOAD_DWORD_OFFSET, 0x3, 366 },
11180 { BUFFER_LOAD_DWORD_OFFSET, 0x4, 384 },
12066 { BUFFER_LOAD_DWORD_OFFSET, 402 },
lib/Target/AMDGPU/SIFrameLowering.cpp 154 TII->get(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), SpillReg)
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 310 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET:
lib/Target/AMDGPU/SIRegisterInfo.cpp 513 return AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
1076 buildSpillLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET,