reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc
 8940     { AArch64::bsub, AArch64::dsub, AArch64::dsub0, AArch64::dsub1, AArch64::dsub2, 0, AArch64::hsub, 0, 0, AArch64::qsub0, AArch64::qsub1, AArch64::qsub2, 0, AArch64::ssub, AArch64::sub_32, AArch64::sub_32, 0, AArch64::subo64_then_sub_32, 0, AArch64::zsub, AArch64::zsub0, AArch64::zsub1, AArch64::zsub2, 0, AArch64::zsub_hi, AArch64::dsub1_then_bsub, AArch64::dsub1_then_hsub, AArch64::dsub1_then_ssub, 0, 0, 0, AArch64::dsub2_then_bsub, AArch64::dsub2_then_hsub, AArch64::dsub2_then_ssub, AArch64::qsub1_then_bsub, AArch64::qsub1_then_dsub, AArch64::qsub1_then_hsub, AArch64::qsub1_then_ssub, 0, 0, 0, 0, AArch64::qsub2_then_bsub, AArch64::qsub2_then_dsub, AArch64::qsub2_then_hsub, AArch64::qsub2_then_ssub, 0, AArch64::zsub1_then_bsub, AArch64::zsub1_then_dsub, AArch64::zsub1_then_hsub, AArch64::zsub1_then_ssub, AArch64::zsub1_then_zsub, AArch64::zsub1_then_zsub_hi, 0, 0, 0, 0, 0, 0, AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, AArch64::zsub2_then_zsub, AArch64::zsub2_then_zsub_hi, AArch64::dsub0_dsub1, 0, AArch64::dsub1_dsub2, 0, 0, AArch64::dsub_qsub1_then_dsub, 0, AArch64::dsub_qsub1_then_dsub_qsub2_then_dsub, AArch64::qsub0_qsub1, 0, AArch64::qsub1_qsub2, 0, 0, AArch64::qsub1_then_dsub_qsub2_then_dsub, 0, 0, 0, AArch64::dsub_zsub1_then_dsub, AArch64::zsub_zsub1_then_zsub, 0, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub, 0, AArch64::zsub_zsub1_then_zsub_zsub2_then_zsub, AArch64::zsub0_zsub1, 0, AArch64::zsub1_zsub2, 0, 0, AArch64::zsub1_then_dsub_zsub2_then_dsub, 0, AArch64::zsub1_then_zsub_zsub2_then_zsub, 0, 0, 0, },
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
 1093   static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1,
 1403   static const unsigned QSubs[] = { AArch64::qsub0, AArch64::qsub1,
 1455     static const unsigned QSubs[] = { AArch64::qsub0, AArch64::qsub1,
 3020         SelectLoad(Node, 2, AArch64::LD1Twov16b, AArch64::qsub0);
 3026         SelectLoad(Node, 2, AArch64::LD1Twov8h, AArch64::qsub0);
 3032         SelectLoad(Node, 2, AArch64::LD1Twov4s, AArch64::qsub0);
 3038         SelectLoad(Node, 2, AArch64::LD1Twov2d, AArch64::qsub0);
 3047         SelectLoad(Node, 3, AArch64::LD1Threev16b, AArch64::qsub0);
 3053         SelectLoad(Node, 3, AArch64::LD1Threev8h, AArch64::qsub0);
 3059         SelectLoad(Node, 3, AArch64::LD1Threev4s, AArch64::qsub0);
 3065         SelectLoad(Node, 3, AArch64::LD1Threev2d, AArch64::qsub0);
 3074         SelectLoad(Node, 4, AArch64::LD1Fourv16b, AArch64::qsub0);
 3080         SelectLoad(Node, 4, AArch64::LD1Fourv8h, AArch64::qsub0);
 3086         SelectLoad(Node, 4, AArch64::LD1Fourv4s, AArch64::qsub0);
 3092         SelectLoad(Node, 4, AArch64::LD1Fourv2d, AArch64::qsub0);
 3101         SelectLoad(Node, 2, AArch64::LD2Twov16b, AArch64::qsub0);
 3107         SelectLoad(Node, 2, AArch64::LD2Twov8h, AArch64::qsub0);
 3113         SelectLoad(Node, 2, AArch64::LD2Twov4s, AArch64::qsub0);
 3119         SelectLoad(Node, 2, AArch64::LD2Twov2d, AArch64::qsub0);
 3128         SelectLoad(Node, 3, AArch64::LD3Threev16b, AArch64::qsub0);
 3134         SelectLoad(Node, 3, AArch64::LD3Threev8h, AArch64::qsub0);
 3140         SelectLoad(Node, 3, AArch64::LD3Threev4s, AArch64::qsub0);
 3146         SelectLoad(Node, 3, AArch64::LD3Threev2d, AArch64::qsub0);
 3155         SelectLoad(Node, 4, AArch64::LD4Fourv16b, AArch64::qsub0);
 3161         SelectLoad(Node, 4, AArch64::LD4Fourv8h, AArch64::qsub0);
 3167         SelectLoad(Node, 4, AArch64::LD4Fourv4s, AArch64::qsub0);
 3173         SelectLoad(Node, 4, AArch64::LD4Fourv2d, AArch64::qsub0);
 3182         SelectLoad(Node, 2, AArch64::LD2Rv16b, AArch64::qsub0);
 3188         SelectLoad(Node, 2, AArch64::LD2Rv8h, AArch64::qsub0);
 3194         SelectLoad(Node, 2, AArch64::LD2Rv4s, AArch64::qsub0);
 3200         SelectLoad(Node, 2, AArch64::LD2Rv2d, AArch64::qsub0);
 3209         SelectLoad(Node, 3, AArch64::LD3Rv16b, AArch64::qsub0);
 3215         SelectLoad(Node, 3, AArch64::LD3Rv8h, AArch64::qsub0);
 3221         SelectLoad(Node, 3, AArch64::LD3Rv4s, AArch64::qsub0);
 3227         SelectLoad(Node, 3, AArch64::LD3Rv2d, AArch64::qsub0);
 3236         SelectLoad(Node, 4, AArch64::LD4Rv16b, AArch64::qsub0);
 3242         SelectLoad(Node, 4, AArch64::LD4Rv8h, AArch64::qsub0);
 3248         SelectLoad(Node, 4, AArch64::LD4Rv4s, AArch64::qsub0);
 3254         SelectLoad(Node, 4, AArch64::LD4Rv2d, AArch64::qsub0);
 3600       SelectPostLoad(Node, 2, AArch64::LD2Twov16b_POST, AArch64::qsub0);
 3606       SelectPostLoad(Node, 2, AArch64::LD2Twov8h_POST, AArch64::qsub0);
 3612       SelectPostLoad(Node, 2, AArch64::LD2Twov4s_POST, AArch64::qsub0);
 3618       SelectPostLoad(Node, 2, AArch64::LD2Twov2d_POST, AArch64::qsub0);
 3628       SelectPostLoad(Node, 3, AArch64::LD3Threev16b_POST, AArch64::qsub0);
 3634       SelectPostLoad(Node, 3, AArch64::LD3Threev8h_POST, AArch64::qsub0);
 3640       SelectPostLoad(Node, 3, AArch64::LD3Threev4s_POST, AArch64::qsub0);
 3646       SelectPostLoad(Node, 3, AArch64::LD3Threev2d_POST, AArch64::qsub0);
 3656       SelectPostLoad(Node, 4, AArch64::LD4Fourv16b_POST, AArch64::qsub0);
 3662       SelectPostLoad(Node, 4, AArch64::LD4Fourv8h_POST, AArch64::qsub0);
 3668       SelectPostLoad(Node, 4, AArch64::LD4Fourv4s_POST, AArch64::qsub0);
 3674       SelectPostLoad(Node, 4, AArch64::LD4Fourv2d_POST, AArch64::qsub0);
 3684       SelectPostLoad(Node, 2, AArch64::LD1Twov16b_POST, AArch64::qsub0);
 3690       SelectPostLoad(Node, 2, AArch64::LD1Twov8h_POST, AArch64::qsub0);
 3696       SelectPostLoad(Node, 2, AArch64::LD1Twov4s_POST, AArch64::qsub0);
 3702       SelectPostLoad(Node, 2, AArch64::LD1Twov2d_POST, AArch64::qsub0);
 3712       SelectPostLoad(Node, 3, AArch64::LD1Threev16b_POST, AArch64::qsub0);
 3718       SelectPostLoad(Node, 3, AArch64::LD1Threev8h_POST, AArch64::qsub0);
 3724       SelectPostLoad(Node, 3, AArch64::LD1Threev4s_POST, AArch64::qsub0);
 3730       SelectPostLoad(Node, 3, AArch64::LD1Threev2d_POST, AArch64::qsub0);
 3740       SelectPostLoad(Node, 4, AArch64::LD1Fourv16b_POST, AArch64::qsub0);
 3746       SelectPostLoad(Node, 4, AArch64::LD1Fourv8h_POST, AArch64::qsub0);
 3752       SelectPostLoad(Node, 4, AArch64::LD1Fourv4s_POST, AArch64::qsub0);
 3758       SelectPostLoad(Node, 4, AArch64::LD1Fourv2d_POST, AArch64::qsub0);
 3768       SelectPostLoad(Node, 1, AArch64::LD1Rv16b_POST, AArch64::qsub0);
 3774       SelectPostLoad(Node, 1, AArch64::LD1Rv8h_POST, AArch64::qsub0);
 3780       SelectPostLoad(Node, 1, AArch64::LD1Rv4s_POST, AArch64::qsub0);
 3786       SelectPostLoad(Node, 1, AArch64::LD1Rv2d_POST, AArch64::qsub0);
 3796       SelectPostLoad(Node, 2, AArch64::LD2Rv16b_POST, AArch64::qsub0);
 3802       SelectPostLoad(Node, 2, AArch64::LD2Rv8h_POST, AArch64::qsub0);
 3808       SelectPostLoad(Node, 2, AArch64::LD2Rv4s_POST, AArch64::qsub0);
 3814       SelectPostLoad(Node, 2, AArch64::LD2Rv2d_POST, AArch64::qsub0);
 3824       SelectPostLoad(Node, 3, AArch64::LD3Rv16b_POST, AArch64::qsub0);
 3830       SelectPostLoad(Node, 3, AArch64::LD3Rv8h_POST, AArch64::qsub0);
 3836       SelectPostLoad(Node, 3, AArch64::LD3Rv4s_POST, AArch64::qsub0);
 3842       SelectPostLoad(Node, 3, AArch64::LD3Rv2d_POST, AArch64::qsub0);
 3852       SelectPostLoad(Node, 4, AArch64::LD4Rv16b_POST, AArch64::qsub0);
 3858       SelectPostLoad(Node, 4, AArch64::LD4Rv8h_POST, AArch64::qsub0);
 3864       SelectPostLoad(Node, 4, AArch64::LD4Rv4s_POST, AArch64::qsub0);
 3870       SelectPostLoad(Node, 4, AArch64::LD4Rv2d_POST, AArch64::qsub0);
lib/Target/AArch64/AArch64InstrInfo.cpp
 2596     static const unsigned Indices[] = {AArch64::qsub0, AArch64::qsub1,
 2606     static const unsigned Indices[] = {AArch64::qsub0, AArch64::qsub1,
 2616     static const unsigned Indices[] = {AArch64::qsub0, AArch64::qsub1};
lib/Target/AArch64/AArch64InstructionSelector.cpp
 3729                     .addImm(AArch64::qsub0)
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
  651       case AArch64::qsub0:
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
 1277   else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))