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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc 2176 /* 4042*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
2216 /* 4143*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
2256 /* 4244*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
2296 /* 4345*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
2336 /* 4446*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
2376 /* 4547*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
2449 /* 4713*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
2503 /* 4855*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
2557 /* 4997*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
2611 /* 5139*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
2665 /* 5281*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
2719 /* 5423*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
2861 /* 5702*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
69696 /*167339*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
69706 /*167365*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
69716 /*167391*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
69726 /*167415*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
69767 /*167492*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
69777 /*167518*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
69787 /*167544*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
69797 /*167568*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
75045 /*177789*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
75059 /*177823*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
75187 /*178059*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
75201 /*178093*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
76599 /*180600*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
76690 /*180779*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
78045 /*183349*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
78059 /*183388*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
78137 /*183600*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
78151 /*183639*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
78233 /*183850*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
78261 /*183906*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
78288 /*183959*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
78807 /*184902*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
78835 /*184958*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
78862 /*185011*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
85145 /*197062*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
85195 /*197179*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
85245 /*197296*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
85335 /*197515*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
85382 /*197627*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
85429 /*197739*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
86268 /*199254*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
86316 /*199365*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
86364 /*199476*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
86410 /*199583*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
86455 /*199689*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
86500 /*199795*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
103758 /*232022*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
103772 /*232062*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
103824 /*232198*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
103838 /*232238*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
103926 /*232462*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
103940 /*232500*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
103992 /*232630*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
104006 /*232668*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
104157 /*232978*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
104177 /*233040*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
104309 /*233434*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
104335 /*233518*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
104364 /*233606*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
104384 /*233666*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
104518 /*234050*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
104544 /*234132*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
106702 /*238347*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
106714 /*238380*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
106728 /*238417*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
106740 /*238450*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
106883 /*238808*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
106895 /*238840*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
107063 /*239242*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
107075 /*239275*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
107089 /*239312*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
107101 /*239345*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
107222 /*239641*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
107230 /*239661*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
110143 /*246035*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
110163 /*246092*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
110784 /*247443*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
110795 /*247474*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
113908 /*253509*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
113918 /*253536*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
113976 /*253688*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
113986 /*253715*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
114034 /*253840*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
114044 /*253867*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
114092 /*253992*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
114102 /*254019*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
114150 /*254144*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
114160 /*254171*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
114208 /*254296*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
114218 /*254323*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 8940 { AArch64::bsub, AArch64::dsub, AArch64::dsub0, AArch64::dsub1, AArch64::dsub2, 0, AArch64::hsub, 0, 0, AArch64::qsub0, AArch64::qsub1, AArch64::qsub2, 0, AArch64::ssub, AArch64::sub_32, AArch64::sub_32, 0, AArch64::subo64_then_sub_32, 0, AArch64::zsub, AArch64::zsub0, AArch64::zsub1, AArch64::zsub2, 0, AArch64::zsub_hi, AArch64::dsub1_then_bsub, AArch64::dsub1_then_hsub, AArch64::dsub1_then_ssub, 0, 0, 0, AArch64::dsub2_then_bsub, AArch64::dsub2_then_hsub, AArch64::dsub2_then_ssub, AArch64::qsub1_then_bsub, AArch64::qsub1_then_dsub, AArch64::qsub1_then_hsub, AArch64::qsub1_then_ssub, 0, 0, 0, 0, AArch64::qsub2_then_bsub, AArch64::qsub2_then_dsub, AArch64::qsub2_then_hsub, AArch64::qsub2_then_ssub, 0, AArch64::zsub1_then_bsub, AArch64::zsub1_then_dsub, AArch64::zsub1_then_hsub, AArch64::zsub1_then_ssub, AArch64::zsub1_then_zsub, AArch64::zsub1_then_zsub_hi, 0, 0, 0, 0, 0, 0, AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, AArch64::zsub2_then_zsub, AArch64::zsub2_then_zsub_hi, AArch64::dsub0_dsub1, 0, AArch64::dsub1_dsub2, 0, 0, AArch64::dsub_qsub1_then_dsub, 0, AArch64::dsub_qsub1_then_dsub_qsub2_then_dsub, AArch64::qsub0_qsub1, 0, AArch64::qsub1_qsub2, 0, 0, AArch64::qsub1_then_dsub_qsub2_then_dsub, 0, 0, 0, AArch64::dsub_zsub1_then_dsub, AArch64::zsub_zsub1_then_zsub, 0, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub, 0, AArch64::zsub_zsub1_then_zsub_zsub2_then_zsub, AArch64::zsub0_zsub1, 0, AArch64::zsub1_zsub2, 0, 0, AArch64::zsub1_then_dsub_zsub2_then_dsub, 0, AArch64::zsub1_then_zsub_zsub2_then_zsub, 0, 0, 0, },
8950 { AArch64::bsub, AArch64::dsub, AArch64::dsub, AArch64::qsub1_then_dsub, AArch64::qsub2_then_dsub, AArch64::qsub3_then_dsub, AArch64::hsub, 0, 0, AArch64::zsub, AArch64::zsub1_then_zsub, AArch64::zsub2_then_zsub, AArch64::zsub3_then_zsub, AArch64::ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::qsub1_then_bsub, AArch64::qsub1_then_hsub, AArch64::qsub1_then_ssub, AArch64::qsub3_then_bsub, AArch64::qsub3_then_hsub, AArch64::qsub3_then_ssub, AArch64::qsub2_then_bsub, AArch64::qsub2_then_hsub, AArch64::qsub2_then_ssub, AArch64::zsub1_then_bsub, AArch64::zsub1_then_dsub, AArch64::zsub1_then_hsub, AArch64::zsub1_then_ssub, AArch64::zsub3_then_bsub, AArch64::zsub3_then_dsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::dsub_qsub1_then_dsub, AArch64::dsub_qsub1_then_dsub_qsub2_then_dsub, AArch64::qsub1_then_dsub_qsub2_then_dsub, AArch64::qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, AArch64::qsub2_then_dsub_qsub3_then_dsub, AArch64::dsub_zsub1_then_dsub, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub_zsub1_then_zsub, AArch64::zsub_zsub1_then_zsub_zsub2_then_zsub, AArch64::zsub1_then_zsub_zsub2_then_zsub, AArch64::zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, AArch64::zsub2_then_zsub_zsub3_then_zsub, AArch64::zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8951 { AArch64::bsub, 0, AArch64::dsub, AArch64::zsub1_then_dsub, AArch64::zsub2_then_dsub, AArch64::zsub3_then_dsub, AArch64::hsub, 0, 0, 0, 0, 0, 0, AArch64::ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::zsub1_then_bsub, AArch64::zsub1_then_hsub, AArch64::zsub1_then_ssub, AArch64::zsub3_then_bsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, AArch64::zsub2_then_bsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::dsub_zsub1_then_dsub, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
lib/Target/AArch64/AArch64ISelLowering.cpp 2610 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
4857 setVecVal(AArch64::hsub);
4876 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, VT, Sel);
11938 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
lib/Target/AArch64/AArch64InstrInfo.cpp 2696 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
2698 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
2704 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
2706 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
lib/Target/AArch64/AArch64InstructionSelector.cpp 376 SubReg = AArch64::hsub;
729 .addImm(AArch64::hsub);
2699 return BuildFn(AArch64::hsub);
2786 ExtractSubReg = AArch64::hsub;
3130 SubregIdx = AArch64::hsub;
lib/Target/AArch64/AArch64RegisterInfo.cpp 104 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub)
106 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub)