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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc 2159 /* 3997*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
2199 /* 4098*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
2239 /* 4199*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
2279 /* 4300*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
2319 /* 4401*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
2359 /* 4502*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
2432 /* 4668*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
2486 /* 4810*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
2540 /* 4952*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
2594 /* 5094*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
2648 /* 5236*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
2702 /* 5378*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
85123 /*197009*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
85173 /*197126*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
85223 /*197243*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
85313 /*197462*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
85360 /*197574*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
85407 /*197686*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
86247 /*199204*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
86295 /*199315*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
86343 /*199426*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
86389 /*199533*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
86434 /*199639*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
86479 /*199745*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
103725 /*231934*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
103739 /*231974*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
103791 /*232110*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
103805 /*232150*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
103893 /*232378*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
103907 /*232416*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
103959 /*232546*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
103973 /*232584*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
104251 /*233253*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
104277 /*233337*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
104460 /*233875*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
104486 /*233957*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
106646 /*238200*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
106658 /*238233*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
106672 /*238270*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
106684 /*238303*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
106855 /*238738*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
106867 /*238770*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
113888 /*253455*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
113898 /*253482*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
113956 /*253634*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
113966 /*253661*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
114014 /*253786*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
114024 /*253813*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
114072 /*253938*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
114082 /*253965*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
114130 /*254090*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
114140 /*254117*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
114188 /*254242*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
114198 /*254269*/ OPC_EmitInteger, MVT::i32, AArch64::bsub,
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 8940 { AArch64::bsub, AArch64::dsub, AArch64::dsub0, AArch64::dsub1, AArch64::dsub2, 0, AArch64::hsub, 0, 0, AArch64::qsub0, AArch64::qsub1, AArch64::qsub2, 0, AArch64::ssub, AArch64::sub_32, AArch64::sub_32, 0, AArch64::subo64_then_sub_32, 0, AArch64::zsub, AArch64::zsub0, AArch64::zsub1, AArch64::zsub2, 0, AArch64::zsub_hi, AArch64::dsub1_then_bsub, AArch64::dsub1_then_hsub, AArch64::dsub1_then_ssub, 0, 0, 0, AArch64::dsub2_then_bsub, AArch64::dsub2_then_hsub, AArch64::dsub2_then_ssub, AArch64::qsub1_then_bsub, AArch64::qsub1_then_dsub, AArch64::qsub1_then_hsub, AArch64::qsub1_then_ssub, 0, 0, 0, 0, AArch64::qsub2_then_bsub, AArch64::qsub2_then_dsub, AArch64::qsub2_then_hsub, AArch64::qsub2_then_ssub, 0, AArch64::zsub1_then_bsub, AArch64::zsub1_then_dsub, AArch64::zsub1_then_hsub, AArch64::zsub1_then_ssub, AArch64::zsub1_then_zsub, AArch64::zsub1_then_zsub_hi, 0, 0, 0, 0, 0, 0, AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, AArch64::zsub2_then_zsub, AArch64::zsub2_then_zsub_hi, AArch64::dsub0_dsub1, 0, AArch64::dsub1_dsub2, 0, 0, AArch64::dsub_qsub1_then_dsub, 0, AArch64::dsub_qsub1_then_dsub_qsub2_then_dsub, AArch64::qsub0_qsub1, 0, AArch64::qsub1_qsub2, 0, 0, AArch64::qsub1_then_dsub_qsub2_then_dsub, 0, 0, 0, AArch64::dsub_zsub1_then_dsub, AArch64::zsub_zsub1_then_zsub, 0, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub, 0, AArch64::zsub_zsub1_then_zsub_zsub2_then_zsub, AArch64::zsub0_zsub1, 0, AArch64::zsub1_zsub2, 0, 0, AArch64::zsub1_then_dsub_zsub2_then_dsub, 0, AArch64::zsub1_then_zsub_zsub2_then_zsub, 0, 0, 0, },
8950 { AArch64::bsub, AArch64::dsub, AArch64::dsub, AArch64::qsub1_then_dsub, AArch64::qsub2_then_dsub, AArch64::qsub3_then_dsub, AArch64::hsub, 0, 0, AArch64::zsub, AArch64::zsub1_then_zsub, AArch64::zsub2_then_zsub, AArch64::zsub3_then_zsub, AArch64::ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::qsub1_then_bsub, AArch64::qsub1_then_hsub, AArch64::qsub1_then_ssub, AArch64::qsub3_then_bsub, AArch64::qsub3_then_hsub, AArch64::qsub3_then_ssub, AArch64::qsub2_then_bsub, AArch64::qsub2_then_hsub, AArch64::qsub2_then_ssub, AArch64::zsub1_then_bsub, AArch64::zsub1_then_dsub, AArch64::zsub1_then_hsub, AArch64::zsub1_then_ssub, AArch64::zsub3_then_bsub, AArch64::zsub3_then_dsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::dsub_qsub1_then_dsub, AArch64::dsub_qsub1_then_dsub_qsub2_then_dsub, AArch64::qsub1_then_dsub_qsub2_then_dsub, AArch64::qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, AArch64::qsub2_then_dsub_qsub3_then_dsub, AArch64::dsub_zsub1_then_dsub, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub_zsub1_then_zsub, AArch64::zsub_zsub1_then_zsub_zsub2_then_zsub, AArch64::zsub1_then_zsub_zsub2_then_zsub, AArch64::zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, AArch64::zsub2_then_zsub_zsub3_then_zsub, AArch64::zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8951 { AArch64::bsub, 0, AArch64::dsub, AArch64::zsub1_then_dsub, AArch64::zsub2_then_dsub, AArch64::zsub3_then_dsub, AArch64::hsub, 0, 0, 0, 0, 0, 0, AArch64::ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::zsub1_then_bsub, AArch64::zsub1_then_hsub, AArch64::zsub1_then_ssub, AArch64::zsub3_then_bsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, AArch64::zsub2_then_bsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::dsub_zsub1_then_dsub, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
lib/Target/AArch64/AArch64InstrInfo.cpp 2717 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
2719 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
2725 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
2727 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
lib/Target/AArch64/AArch64InstructionSelector.cpp 373 SubReg = AArch64::bsub;
3127 SubregIdx = AArch64::bsub;