|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6506 static const MCOperandInfo OperandInfo105[] = { { AArch64::XSeqPairsClassRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::XSeqPairsClassRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::XSeqPairsClassRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6506 static const MCOperandInfo OperandInfo105[] = { { AArch64::XSeqPairsClassRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::XSeqPairsClassRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::XSeqPairsClassRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6506 static const MCOperandInfo OperandInfo105[] = { { AArch64::XSeqPairsClassRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::XSeqPairsClassRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::XSeqPairsClassRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 3465 { XSeqPairsClass, XSeqPairsClassBits, 2570, 16, sizeof(XSeqPairsClassBits), AArch64::XSeqPairsClassRegClassID, 1, true },
7230 &AArch64MCRegisterClasses[XSeqPairsClassRegClassID],
lib/Target/AArch64/AArch64ISelLowering.cpp11977 DAG.getTargetConstant(AArch64::XSeqPairsClassRegClassID, dl, MVT::i32);
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 258 case AArch64::XSeqPairsClassRegClassID:
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 1128 AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID].contains(
5649 &AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID]);
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp 1804 AArch64::XSeqPairsClassRegClassID,