|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc11255 case AArch64::SP: OpKind = MCK_GPR64sponly; break;
gen/lib/Target/AArch64/AArch64GenDAGISel.inc92025 /*209742*/ OPC_EmitRegister, MVT::i64, AArch64::SP,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc36285 GIR_AddRegister, /*InsnID*/0, AArch64::SP, /*AddRegisterRegFlags*/0,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6393 static const MCPhysReg ImplicitList2[] = { AArch64::SP, 0 };
6396 static const MCPhysReg ImplicitList5[] = { AArch64::LR, AArch64::SP, 0 };
18289 || MI.getOperand(0).getReg() == AArch64::SP
18291 || MI.getOperand(1).getReg() == AArch64::SP
30027 || MI.getOperand(0).getReg() == AArch64::SP
30029 || MI.getOperand(1).getReg() == AArch64::SP
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 2430 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::SP,
2460 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP,
2540 AArch64::SP,
3786 { AArch64::SP, 31U },
4065 { AArch64::SP, 31U },
6867 static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
20422 static const MCPhysReg CSR_AArch64_AllRegs_SaveList[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20424 static const MCPhysReg CSR_AArch64_AllRegs_SCS_SaveList[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20444 static const MCPhysReg CSR_AArch64_StackProbe_Windows_SaveList[] = { AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::SP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
lib/Target/AArch64/AArch64AsmPrinter.cpp 401 .addReg(AArch64::SP)
404 .addReg(AArch64::SP)
410 .addReg(AArch64::SP)
lib/Target/AArch64/AArch64CallLowering.cpp 157 MIRBuilder.buildCopy(SPReg, Register(AArch64::SP));
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 646 if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP)
lib/Target/AArch64/AArch64FastISel.cpp 1320 if (LHSReg == AArch64::SP || LHSReg == AArch64::WSP ||
1321 RHSReg == AArch64::SP || RHSReg == AArch64::WSP)
1404 assert(LHSReg != AArch64::SP && LHSReg != AArch64::WSP &&
1405 RHSReg != AArch64::SP && RHSReg != AArch64::WSP);
3137 Addr.setReg(AArch64::SP);
lib/Target/AArch64/AArch64FrameLowering.cpp 306 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, {Amount, MVT::i8},
306 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, {Amount, MVT::i8},
313 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP,
313 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP,
635 assert(MBBI->getOperand(0).getReg() != AArch64::SP);
694 MIB.addReg(AArch64::SP, RegState::Define);
705 assert(MBBI->getOperand(OpndIdx - 1).getReg() == AArch64::SP &&
739 assert(MI.getOperand(0).getReg() != AArch64::SP);
766 assert(MI.getOperand(OffsetIdx - 1).getReg() == AArch64::SP &&
916 emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP,
916 emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP,
953 emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP,
953 emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP,
1011 emitFrameOffset(MBB, MBBI, DL, AArch64::FP, AArch64::SP,
1096 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SUBXrx64), AArch64::SP)
1097 .addReg(AArch64::SP, RegState::Kill)
1110 emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -SVEStackSize, TII,
1110 emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -SVEStackSize, TII,
1116 unsigned scratchSPReg = AArch64::SP;
1128 emitFrameOffset(MBB, MBBI, DL, scratchSPReg, AArch64::SP,
1136 assert(scratchSPReg != AArch64::SP);
1149 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ANDXri), AArch64::SP)
1170 TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP,
1466 emitFrameOffset(MBB, MBB.getFirstTerminator(), DL, AArch64::SP, AArch64::SP,
1466 emitFrameOffset(MBB, MBB.getFirstTerminator(), DL, AArch64::SP, AArch64::SP,
1482 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP, SVEStackSize,
1482 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP, SVEStackSize,
1505 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP,
1505 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP,
1528 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::FP,
1532 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP,
1532 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP,
1547 Prev->getOperand(0).getReg() == AArch64::SP)
1554 emitFrameOffset(MBB, FirstSPPopI, DL, AArch64::SP, AArch64::SP,
1554 emitFrameOffset(MBB, FirstSPPopI, DL, AArch64::SP, AArch64::SP,
1725 : (unsigned)AArch64::SP;
1746 FrameReg = AArch64::SP;
2058 .addReg(AArch64::SP)
2143 .addReg(AArch64::SP)
2394 FrameReg = AArch64::SP;
lib/Target/AArch64/AArch64ISelLowering.cpp 637 setStackPointerRegisterToSaveRestore(AArch64::SP);
3843 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP,
8327 SDValue SP = DAG.getCopyFromReg(Chain, dl, AArch64::SP, MVT::i64);
8333 Chain = DAG.getCopyToReg(Chain, dl, AArch64::SP, SP);
8342 SDValue SP = DAG.getCopyFromReg(Chain, dl, AArch64::SP, MVT::i64);
8348 Chain = DAG.getCopyToReg(Chain, dl, AArch64::SP, SP);
lib/Target/AArch64/AArch64InstrInfo.cpp 2545 if (DestReg == AArch64::SP || SrcReg == AArch64::SP) {
2545 if (DestReg == AArch64::SP || SrcReg == AArch64::SP) {
2646 .addReg(AArch64::SP, RegState::Define)
2648 .addReg(AArch64::SP)
2651 .addReg(AArch64::SP, RegState::Define)
2653 .addReg(AArch64::SP)
2843 assert(SrcReg != AArch64::SP);
2974 assert(DestReg != AArch64::SP);
3107 if ((DestReg == AArch64::FP && SrcReg == AArch64::SP) ||
3108 (SrcReg == AArch64::FP && DestReg == AArch64::SP)) {
3119 } else if (DestReg == AArch64::SP) {
3122 assert(SrcReg == AArch64::SP && "Unexpected SrcReg for SEH_StackAlloc");
3147 assert((DestReg != AArch64::SP || Bytes % 16 == 0) &&
3171 assert(DestReg != AArch64::SP && "Unaligned access to SP");
3197 if (SrcReg == AArch64::SP && Register::isVirtualRegister(DstReg)) {
3201 if (DstReg == AArch64::SP && Register::isVirtualRegister(SrcReg)) {
5121 if (!MI.modifiesRegister(AArch64::SP, &TRI) &&
5122 !MI.readsRegister(AArch64::SP, &TRI))
5128 if (MI.modifiesRegister(AArch64::SP, &TRI))
5140 Base->getReg() != AArch64::SP)
5213 else if (C.UsedInSequence.available(AArch64::SP)) {
5511 (Base->isReg() && Base->getReg() != AArch64::SP))
5575 .addReg(AArch64::SP, RegState::Define)
5577 .addReg(AArch64::SP)
5602 .addReg(AArch64::SP, RegState::Define)
5604 .addReg(AArch64::SP)
5676 .addReg(AArch64::SP, RegState::Define)
5678 .addReg(AArch64::SP)
5681 .addReg(AArch64::SP, RegState::Define)
5683 .addReg(AArch64::SP)
lib/Target/AArch64/AArch64RegisterInfo.cpp 293 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
387 if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
514 FrameReg = AArch64::SP;
581 return AArch64::SP;
lib/Target/AArch64/AArch64SelectionDAGInfo.cpp 75 TagSrc = DAG.getRegister(AArch64::SP, MVT::i64);
lib/Target/AArch64/AArch64SpeculationHardening.cpp 371 .addUse(AArch64::SP)
394 .addUse(AArch64::SP)
405 .addDef(AArch64::SP)
441 if (Reg == AArch64::SP || Reg == AArch64::WSP)
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 4084 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
4098 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp 457 Register = AArch64::SP;
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 996 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
996 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp 128 {codeview::RegisterId::ARM64_SP, AArch64::SP},
256 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
lib/Target/AArch64/Utils/AArch64BaseInfo.h 62 case AArch64::SP: return AArch64::WSP;
102 case AArch64::WSP: return AArch64::SP;