|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc18249 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18275 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18314 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18340 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18485 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18511 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18550 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18576 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18589 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18602 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18641 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18667 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18696 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18709 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18722 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18735 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
23997 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24023 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24062 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24088 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24247 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24260 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24299 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24325 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24354 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24367 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24380 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24393 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc18965 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
18991 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
19030 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
19056 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
19201 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
19227 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
19266 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
19292 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
19305 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
19318 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
19357 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
19383 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
19412 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
19425 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
19438 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
19451 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24713 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24739 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24778 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24804 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24963 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
24976 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
25015 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
25041 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
25070 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
25083 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
25096 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
25109 MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) &&
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6671 static const MCOperandInfo OperandInfo270[] = { { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6672 static const MCOperandInfo OperandInfo271[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6679 static const MCOperandInfo OperandInfo278[] = { { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6679 static const MCOperandInfo OperandInfo278[] = { { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6680 static const MCOperandInfo OperandInfo279[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6680 static const MCOperandInfo OperandInfo279[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6805 static const MCOperandInfo OperandInfo404[] = { { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6806 static const MCOperandInfo OperandInfo405[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6826 static const MCOperandInfo OperandInfo425[] = { { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6830 static const MCOperandInfo OperandInfo429[] = { { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6835 static const MCOperandInfo OperandInfo434[] = { { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6839 static const MCOperandInfo OperandInfo438[] = { { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::QQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
gen/lib/Target/AArch64/AArch64GenRegisterBank.inc 60 (1u << (AArch64::QQRegClassID - 32)) |
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 3482 { QQ, QQBits, 277, 32, sizeof(QQBits), AArch64::QQRegClassID, 1, true },
7434 &AArch64MCRegisterClasses[QQRegClassID],
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 1092 AArch64::QQRegClassID, AArch64::QQQRegClassID, AArch64::QQQQRegClassID};
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 73 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
237 case AArch64::QQRegClassID:
lib/Target/AArch64/AArch64RegisterInfo.cpp 567 case AArch64::QQRegClassID:
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 1263 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))