|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc18145 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18171 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18210 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18236 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18796 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18822 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18861 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18887 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18900 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18913 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18952 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18978 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19007 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19020 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19033 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19046 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
23893 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
23919 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
23958 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
23984 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24454 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24467 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24506 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24532 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24561 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24574 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24587 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24600 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc18861 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18887 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18926 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18952 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19512 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19538 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19577 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19603 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19616 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19629 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19668 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19694 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19723 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19736 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19749 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19762 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24609 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24635 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24674 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24700 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25170 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25183 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25222 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25248 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25277 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25290 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25303 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25316 MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) &&
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6667 static const MCOperandInfo OperandInfo266[] = { { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6668 static const MCOperandInfo OperandInfo267[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6683 static const MCOperandInfo OperandInfo282[] = { { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6683 static const MCOperandInfo OperandInfo282[] = { { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6684 static const MCOperandInfo OperandInfo283[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6684 static const MCOperandInfo OperandInfo283[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6807 static const MCOperandInfo OperandInfo406[] = { { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6808 static const MCOperandInfo OperandInfo407[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6825 static const MCOperandInfo OperandInfo424[] = { { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6829 static const MCOperandInfo OperandInfo428[] = { { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6834 static const MCOperandInfo OperandInfo433[] = { { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6838 static const MCOperandInfo OperandInfo437[] = { { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::QQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
gen/lib/Target/AArch64/AArch64GenRegisterBank.inc 61 (1u << (AArch64::QQQRegClassID - 32)) |
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 3493 { QQQ, QQQBits, 276, 32, sizeof(QQQBits), AArch64::QQQRegClassID, 1, true },
7566 &AArch64MCRegisterClasses[QQQRegClassID],
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 1092 AArch64::QQRegClassID, AArch64::QQQRegClassID, AArch64::QQQQRegClassID};
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 238 case AArch64::QQQRegClassID:
lib/Target/AArch64/AArch64RegisterInfo.cpp 568 case AArch64::QQQRegClassID:
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 1267 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))