|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc17369 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
17395 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
17434 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
17460 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19091 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19104 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19143 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19169 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19198 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19224 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19263 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19289 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19318 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19331 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19344 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19357 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
23637 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
23663 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
23702 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
23728 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24645 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24658 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24697 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24723 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24768 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24781 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24794 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24807 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc18085 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18111 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18150 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
18176 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19807 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19820 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19859 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19885 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19914 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19940 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
19979 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
20005 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
20034 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
20047 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
20060 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
20073 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24353 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24379 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24418 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
24444 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25361 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25374 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25413 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25439 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25484 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25497 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25510 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
25523 MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) &&
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6659 static const MCOperandInfo OperandInfo258[] = { { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6660 static const MCOperandInfo OperandInfo259[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6687 static const MCOperandInfo OperandInfo286[] = { { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6687 static const MCOperandInfo OperandInfo286[] = { { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6688 static const MCOperandInfo OperandInfo287[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6688 static const MCOperandInfo OperandInfo287[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6809 static const MCOperandInfo OperandInfo408[] = { { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6810 static const MCOperandInfo OperandInfo409[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6824 static const MCOperandInfo OperandInfo423[] = { { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6827 static const MCOperandInfo OperandInfo426[] = { { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6833 static const MCOperandInfo OperandInfo432[] = { { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6836 static const MCOperandInfo OperandInfo435[] = { { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::QQQQRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
gen/lib/Target/AArch64/AArch64GenRegisterBank.inc 71 (1u << (AArch64::QQQQRegClassID - 64)) |
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 3513 { QQQQ, QQQQBits, 275, 32, sizeof(QQQQBits), AArch64::QQQQRegClassID, 1, true },
7806 &AArch64MCRegisterClasses[QQQQRegClassID],
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 1092 AArch64::QQRegClassID, AArch64::QQQRegClassID, AArch64::QQQQRegClassID};
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 239 case AArch64::QQQQRegClassID:
lib/Target/AArch64/AArch64RegisterInfo.cpp 569 case AArch64::QQQQRegClassID:
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 1271 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))