|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc11257 case AArch64::NZCV: OpKind = MCK_CCR; break;
gen/lib/Target/AArch64/AArch64GenDAGISel.inc92900 /*211400*/ OPC_EmitCopyToReg, 1, AArch64::NZCV,
92909 /*211422*/ OPC_EmitCopyToReg, 1, AArch64::NZCV,
92927 /*211467*/ OPC_EmitCopyToReg, 1, AArch64::NZCV,
92936 /*211489*/ OPC_EmitCopyToReg, 1, AArch64::NZCV,
92958 /*211527*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
92965 /*211543*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
92987 /*211583*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
92995 /*211602*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93016 /*211648*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93023 /*211664*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93045 /*211713*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93053 /*211732*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93074 /*211769*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93081 /*211785*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93103 /*211825*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93111 /*211844*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93129 /*211878*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
93137 /*211897*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
93156 /*211934*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
93165 /*211956*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
93183 /*211999*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
93191 /*212018*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
93210 /*212064*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
93219 /*212086*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
93236 /*212116*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93243 /*212132*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93251 /*212150*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93259 /*212168*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93267 /*212186*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93274 /*212202*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
93601 /*212950*/ OPC_EmitCopyToReg, 4, AArch64::NZCV,
93620 /*212985*/ OPC_EmitCopyToReg, 4, AArch64::NZCV,
93648 /*213035*/ OPC_EmitCopyToReg, 4, AArch64::NZCV,
93667 /*213070*/ OPC_EmitCopyToReg, 4, AArch64::NZCV,
93698 /*213127*/ OPC_EmitCopyToReg, 4, AArch64::NZCV,
93717 /*213162*/ OPC_EmitCopyToReg, 4, AArch64::NZCV,
93745 /*213212*/ OPC_EmitCopyToReg, 4, AArch64::NZCV,
93764 /*213247*/ OPC_EmitCopyToReg, 4, AArch64::NZCV,
95033 /*215657*/ OPC_EmitCopyToReg, 4, AArch64::NZCV,
95055 /*215697*/ OPC_EmitCopyToReg, 4, AArch64::NZCV,
95077 /*215737*/ OPC_EmitCopyToReg, 4, AArch64::NZCV,
96106 /*217658*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
96113 /*217674*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
96130 /*217706*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
96137 /*217722*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
96154 /*217754*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
96161 /*217770*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
96271 /*217967*/ OPC_EmitCopyToReg, 3, AArch64::NZCV,
98951 /*222984*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
98957 /*222997*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
98968 /*223018*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
98974 /*223032*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
98985 /*223054*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
98991 /*223067*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
99002 /*223088*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
99008 /*223102*/ OPC_EmitCopyToReg, 2, AArch64::NZCV,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 4157 GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV,
4519 GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6392 static const MCPhysReg ImplicitList1[] = { AArch64::NZCV, 0 };
6400 static const MCPhysReg ImplicitList9[] = { AArch64::X16, AArch64::X17, AArch64::LR, AArch64::NZCV, 0 };
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 2163 { AArch64::NZCV },
2380 AArch64::NZCV,
lib/Target/AArch64/AArch64CondBrTuning.cpp 94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
199 if (I->modifiesRegister(AArch64::NZCV, TRI) ||
200 I->readsRegister(AArch64::NZCV, TRI))
258 if (I->modifiesRegister(AArch64::NZCV, TRI) ||
259 I->readsRegister(AArch64::NZCV, TRI))
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 156 if (SuccBB->isLiveIn(AArch64::NZCV))
164 if (I->readsRegister(AArch64::NZCV))
lib/Target/AArch64/AArch64ConditionalCompares.cpp 303 if (!I->readsRegister(AArch64::NZCV)) {
355 MIOperands(*I).analyzePhysReg(AArch64::NZCV, TRI);
427 if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 212 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
lib/Target/AArch64/AArch64FrameLowering.cpp 1061 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define | RegState::Dead)
1086 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define | RegState::Dead)
lib/Target/AArch64/AArch64ISelLowering.cpp 1367 TrueBB->addLiveIn(AArch64::NZCV);
1368 EndBB->addLiveIn(AArch64::NZCV);
6024 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
lib/Target/AArch64/AArch64InstrInfo.cpp 444 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
472 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
1163 Instr.modifiesRegister(AArch64::NZCV, TRI)) ||
1164 ((AccessToCheck & AK_Read) && Instr.readsRegister(AArch64::NZCV, TRI)))
1188 int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true);
1275 if (BB->isLiveIn(AArch64::NZCV))
1310 int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
1325 int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
1422 if (Instr.readsRegister(AArch64::NZCV, TRI)) {
1429 if (Instr.modifiesRegister(AArch64::NZCV, TRI))
1464 MI->addRegisterDefined(AArch64::NZCV, TRI);
2762 if (DestReg == AArch64::NZCV) {
2767 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define);
2771 if (SrcReg == AArch64::NZCV) {
2775 .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));
3673 int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true);
4861 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1)
5079 !LRU.available(AArch64::NZCV));
5319 bool NZCVAvailableInBlock = LRU.available(AArch64::NZCV);
5335 if (NZCVAvailableInBlock && !LRU.available(AArch64::NZCV))
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 269 if (PredI.definesRegister(AArch64::NZCV))
lib/Target/AArch64/AArch64SpeculationHardening.cpp 236 SplitEdgeBB.addLiveIn(AArch64::NZCV);
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp 130 {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV},