reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
14856 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && 14879 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && 14988 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(0).getReg()) && 15003 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && 15031 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(0).getReg()) && 15046 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && 25788 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && 25811 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && 25979 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(0).getReg()) && 25994 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) &&gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc
15572 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && 15595 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && 15704 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(0).getReg()) && 15719 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && 15747 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(0).getReg()) && 15762 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && 26504 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && 26527 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && 26695 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(0).getReg()) && 26710 MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) &&gen/lib/Target/AArch64/AArch64GenRegisterBank.inc
107 (1u << (AArch64::GPR32sponlyRegClassID - 0)) |
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc3448 { GPR32sponly, GPR32sponlyBits, 2585, 1, sizeof(GPR32sponlyBits), AArch64::GPR32sponlyRegClassID, 1, true }, 7026 &AArch64MCRegisterClasses[GPR32sponlyRegClassID],lib/Target/AArch64/AArch64RegisterBankInfo.cpp
244 case AArch64::GPR32sponlyRegClassID: