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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc14809 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg())) {
14868 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
14990 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
15001 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(0).getReg()) &&
15033 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
15044 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(0).getReg()) &&
15532 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(3).getReg()) &&
15560 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(3).getReg()) &&
15574 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(3).getReg()) &&
16157 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
16181 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
16193 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
25719 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg())) {
25800 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
25981 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
25992 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(0).getReg()) &&
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc15525 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg())) {
15584 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
15706 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
15717 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(0).getReg()) &&
15749 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
15760 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(0).getReg()) &&
16248 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(3).getReg()) &&
16276 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(3).getReg()) &&
16290 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(3).getReg()) &&
16873 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
16897 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
16909 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
26435 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg())) {
26516 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
26697 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) &&
26708 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(0).getReg()) &&
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 1125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
1126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID,
1139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
1140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
1153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
1154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID,
1181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
1182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
4097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
4110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
4125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
5655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
6252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
6749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6454 static const MCOperandInfo OperandInfo53[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6456 static const MCOperandInfo OperandInfo55[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6466 static const MCOperandInfo OperandInfo65[] = { { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6466 static const MCOperandInfo OperandInfo65[] = { { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6467 static const MCOperandInfo OperandInfo66[] = { { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6467 static const MCOperandInfo OperandInfo66[] = { { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6484 static const MCOperandInfo OperandInfo83[] = { { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6533 static const MCOperandInfo OperandInfo132[] = { { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6552 static const MCOperandInfo OperandInfo151[] = { { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
gen/lib/Target/AArch64/AArch64GenRegisterBank.inc 96 (1u << (AArch64::GPR32spRegClassID - 0)) |
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 3444 { GPR32sp, GPR32spBits, 2539, 32, sizeof(GPR32spBits), AArch64::GPR32spRegClassID, 1, true },
6826 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32spRegClassID];
6978 &AArch64MCRegisterClasses[GPR32spRegClassID],
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 243 case AArch64::GPR32spRegClassID:
lib/Target/AArch64/AArch64RegisterInfo.cpp 546 case AArch64::GPR32spRegClassID: