|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc14819 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
14821 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
14831 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
14833 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
14840 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
14842 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
14844 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
14858 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
14870 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
14877 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
14881 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
14942 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
15016 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15018 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15020 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15035 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15048 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15131 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg())) {
15141 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15143 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15153 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15155 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
15162 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15164 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15166 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15240 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15242 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15244 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15315 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15317 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15319 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15345 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15347 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15349 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15688 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15698 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15700 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15736 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15746 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15748 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15784 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15786 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
16323 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
16325 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
16327 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
16369 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
16371 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
16373 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
16444 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
16446 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
17171 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(3).getReg()) &&
17195 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(3).getReg()) &&
17243 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(3).getReg()) &&
19369 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19382 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19395 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19408 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19421 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19447 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19472 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
19486 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
19500 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
19528 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
19584 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
19599 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19612 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19625 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19638 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19651 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19677 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19703 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19716 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19729 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19742 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19755 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
19781 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20361 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
20363 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20695 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
20697 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20753 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
20770 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
20843 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
20860 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
20933 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
20950 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
20993 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21010 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21113 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21130 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21202 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21215 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21228 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21241 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21254 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21280 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21306 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21319 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21332 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21345 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21358 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21384 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21410 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21423 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21436 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21449 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21462 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21488 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21513 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21526 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21539 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21565 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21604 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21631 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21644 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21657 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21670 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21683 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21709 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21735 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21748 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21761 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21774 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21787 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21813 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21838 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21877 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21916 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21942 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21994 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22020 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22022 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22024 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
22048 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22050 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22052 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
22098 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22101 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
22110 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22113 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
22120 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22122 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22124 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
22188 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22191 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
22200 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22202 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22204 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
22636 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22639 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
22660 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22663 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
22684 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22686 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22695 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22697 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22708 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22710 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22857 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22859 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
22871 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22873 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
24848 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
24862 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
24876 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
24949 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
24951 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
25193 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25195 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
25223 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25240 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25313 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25330 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25433 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25450 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25521 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25534 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25547 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25573 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25612 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25664 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25729 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
25731 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
25741 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
25743 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
25750 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25753 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
25762 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25765 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
25772 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25774 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
25776 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
25790 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
25802 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
25809 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25813 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
25896 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
25942 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25945 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
25954 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25957 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
25964 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25966 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
25968 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
25983 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
25996 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
26080 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26082 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
26091 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26093 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
26104 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26106 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
26173 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
26175 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
26185 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26211 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
26213 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
26223 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26235 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26271 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26283 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26343 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26355 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26415 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26427 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26487 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26499 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26535 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26547 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26607 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26619 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26679 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26691 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc15535 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15537 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15547 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15549 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
15556 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15558 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15560 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15574 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15586 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
15593 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15597 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15658 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
15732 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15734 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15736 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15751 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15764 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15847 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg())) {
15857 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15859 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15869 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15871 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
15878 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15880 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15882 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
15956 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
15958 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
15960 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
16031 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
16033 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
16035 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
16061 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
16063 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
16065 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
16404 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
16414 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
16416 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
16452 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
16462 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
16464 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
16500 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
16502 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
17039 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
17041 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
17043 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
17085 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
17087 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
17089 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
17160 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
17162 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
17887 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(3).getReg()) &&
17911 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(3).getReg()) &&
17959 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(3).getReg()) &&
20085 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20098 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20111 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20124 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20137 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20163 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20188 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
20202 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
20216 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
20244 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
20300 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
20315 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20328 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20341 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20354 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20367 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20393 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20419 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20432 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20445 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20458 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20471 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
20497 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21077 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21079 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21411 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21413 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21469 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21486 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21559 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21576 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21649 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21666 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21709 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21726 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21829 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21846 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
21918 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21931 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21944 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21957 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21970 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
21996 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22022 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22035 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22048 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22061 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22074 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22100 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22126 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22139 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22152 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22165 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22178 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22204 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22229 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22242 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22255 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22281 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22320 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22347 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22360 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22373 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22386 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22399 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22425 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22451 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22464 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22477 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22490 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22503 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22529 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22554 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22593 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22632 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22658 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22710 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22736 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22738 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22740 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
22764 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22766 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22768 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
22814 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22817 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
22826 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22829 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
22836 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22838 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22840 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
22904 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22907 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
22916 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
22918 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
22920 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
23352 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
23355 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
23376 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
23379 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
23400 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
23402 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
23411 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
23413 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
23424 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
23426 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
23573 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
23575 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
23587 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
23589 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
25564 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25578 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25592 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25665 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25667 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
25909 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25911 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
25939 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
25956 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26029 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26046 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26149 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26166 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26237 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26250 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26263 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26289 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26328 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26380 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26445 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
26447 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
26457 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
26459 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
26466 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26469 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
26478 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26481 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
26488 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26490 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
26492 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
26506 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
26518 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
26525 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26529 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
26612 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
26658 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26661 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
26670 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26673 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
26680 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26682 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
26684 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
26699 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
26712 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
26796 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26798 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
26807 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26809 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
26820 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26822 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
26889 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
26891 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
26901 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26927 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
26929 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
26939 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26951 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26987 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
26999 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
27059 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
27071 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
27131 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
27143 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
27203 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
27215 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
27251 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
27263 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
27323 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
27335 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
27395 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
27407 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
gen/lib/Target/AArch64/AArch64GenDAGISel.inc100606 /*225983*/ OPC_EmitInteger, MVT::i32, AArch64::GPR32RegClassID,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 1167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
1168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
1195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
1196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
1210 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
1223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
1224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
1238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
1326 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1361 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1411 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1446 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1480 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1484 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1509 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1513 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1539 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1543 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1568 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
1572 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
4081 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4082 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
4096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
4111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
4138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
4139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
4153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
4179 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4214 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4249 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4253 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4278 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4282 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4307 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4342 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4377 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4381 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4406 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
4410 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
5176 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
5177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
5191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5197 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
5211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5212 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
5276 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5304 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5332 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5336 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5354 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5358 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
5490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
5523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
5524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
5565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
5571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
5585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
5586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
5630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
5656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5674 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
5675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
5688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
5689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
5707 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
5722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
5723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5728 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
5743 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
5744 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
6212 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
6232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
6285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6299 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6304 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
6319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6325 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
6629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6634 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
6669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6674 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
6689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6694 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6714 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6729 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6750 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6769 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
6782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6801 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
6816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6821 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6822 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
6836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6842 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6856 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
6871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
6872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
9459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
9467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13610 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13718 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13750 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
13764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15143 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15482 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
15533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
16163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
16195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
16225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
17767 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17951 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
17987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
17991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18011 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18051 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18647 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18729 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18833 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18855 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
18959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
18963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19743 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19767 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
19943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
19947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20117 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20141 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20591 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20969 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
20985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
20989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21543 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21793 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21833 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21897 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
21993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
21997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
22013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
22238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22926 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
22990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
25101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
25102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
25612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
25646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
28249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
28250 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
28251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
28268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
28269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
28270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
28287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
28288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
28289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
28306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
28307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
28325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
28326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
28327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
28344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
28345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
28346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
28363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
28364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
28365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
28382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
28383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
34233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
34234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
34235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
34269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
34270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID,
34271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID,
36301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36309 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
36332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36340 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
36363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36371 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
36394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36402 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
36425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36627 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
36648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36652 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
36742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36769 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36844 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
36974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
37252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
37529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37534 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37550 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37566 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37591 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37615 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
37657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37680 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37696 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37712 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37755 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37779 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
37821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37844 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37860 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37876 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37900 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37956 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
37981 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
40952 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
40968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
40984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
41000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
41017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
41028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
41039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
41226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
41242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
41258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
41274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
41291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
41302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
41313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
41503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
41527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
41551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
41652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
41794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
42054 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
43142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
43164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
43186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
43281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
43282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
43333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
43350 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
43382 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
43405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
43619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
43620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
43649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
43650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6443 static const MCOperandInfo OperandInfo42[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6443 static const MCOperandInfo OperandInfo42[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6443 static const MCOperandInfo OperandInfo42[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6454 static const MCOperandInfo OperandInfo53[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6455 static const MCOperandInfo OperandInfo54[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6455 static const MCOperandInfo OperandInfo54[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6455 static const MCOperandInfo OperandInfo54[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6456 static const MCOperandInfo OperandInfo55[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6456 static const MCOperandInfo OperandInfo55[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6459 static const MCOperandInfo OperandInfo58[] = { { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6467 static const MCOperandInfo OperandInfo66[] = { { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6468 static const MCOperandInfo OperandInfo67[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6477 static const MCOperandInfo OperandInfo76[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6477 static const MCOperandInfo OperandInfo76[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6484 static const MCOperandInfo OperandInfo83[] = { { AArch64::GPR32spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6493 static const MCOperandInfo OperandInfo92[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6493 static const MCOperandInfo OperandInfo92[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6493 static const MCOperandInfo OperandInfo92[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6503 static const MCOperandInfo OperandInfo102[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6503 static const MCOperandInfo OperandInfo102[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6503 static const MCOperandInfo OperandInfo102[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6507 static const MCOperandInfo OperandInfo106[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
6509 static const MCOperandInfo OperandInfo108[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6510 static const MCOperandInfo OperandInfo109[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6510 static const MCOperandInfo OperandInfo109[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6516 static const MCOperandInfo OperandInfo115[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6516 static const MCOperandInfo OperandInfo115[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6522 static const MCOperandInfo OperandInfo121[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6522 static const MCOperandInfo OperandInfo121[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6526 static const MCOperandInfo OperandInfo125[] = { { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6527 static const MCOperandInfo OperandInfo126[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6527 static const MCOperandInfo OperandInfo126[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6527 static const MCOperandInfo OperandInfo126[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6527 static const MCOperandInfo OperandInfo126[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6528 static const MCOperandInfo OperandInfo127[] = { { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6544 static const MCOperandInfo OperandInfo143[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6544 static const MCOperandInfo OperandInfo143[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6545 static const MCOperandInfo OperandInfo144[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6545 static const MCOperandInfo OperandInfo144[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6545 static const MCOperandInfo OperandInfo144[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6554 static const MCOperandInfo OperandInfo153[] = { { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6556 static const MCOperandInfo OperandInfo155[] = { { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6584 static const MCOperandInfo OperandInfo183[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6585 static const MCOperandInfo OperandInfo184[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6586 static const MCOperandInfo OperandInfo185[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6595 static const MCOperandInfo OperandInfo194[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6596 static const MCOperandInfo OperandInfo195[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6597 static const MCOperandInfo OperandInfo196[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6620 static const MCOperandInfo OperandInfo219[] = { { AArch64::FPR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6621 static const MCOperandInfo OperandInfo220[] = { { AArch64::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6638 static const MCOperandInfo OperandInfo237[] = { { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6640 static const MCOperandInfo OperandInfo239[] = { { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6642 static const MCOperandInfo OperandInfo241[] = { { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6642 static const MCOperandInfo OperandInfo241[] = { { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6644 static const MCOperandInfo OperandInfo243[] = { { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6650 static const MCOperandInfo OperandInfo249[] = { { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6655 static const MCOperandInfo OperandInfo254[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6689 static const MCOperandInfo OperandInfo288[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6689 static const MCOperandInfo OperandInfo288[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6691 static const MCOperandInfo OperandInfo290[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6692 static const MCOperandInfo OperandInfo291[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6699 static const MCOperandInfo OperandInfo298[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6699 static const MCOperandInfo OperandInfo298[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6706 static const MCOperandInfo OperandInfo305[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6706 static const MCOperandInfo OperandInfo305[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6708 static const MCOperandInfo OperandInfo307[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6709 static const MCOperandInfo OperandInfo308[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6709 static const MCOperandInfo OperandInfo308[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6710 static const MCOperandInfo OperandInfo309[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6712 static const MCOperandInfo OperandInfo311[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6717 static const MCOperandInfo OperandInfo316[] = { { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6721 static const MCOperandInfo OperandInfo320[] = { { AArch64::FPR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6726 static const MCOperandInfo OperandInfo325[] = { { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6729 static const MCOperandInfo OperandInfo328[] = { { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6733 static const MCOperandInfo OperandInfo332[] = { { AArch64::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6739 static const MCOperandInfo OperandInfo338[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6739 static const MCOperandInfo OperandInfo338[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6739 static const MCOperandInfo OperandInfo338[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6739 static const MCOperandInfo OperandInfo338[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6743 static const MCOperandInfo OperandInfo342[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6743 static const MCOperandInfo OperandInfo342[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6744 static const MCOperandInfo OperandInfo343[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6746 static const MCOperandInfo OperandInfo345[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
6755 static const MCOperandInfo OperandInfo354[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6764 static const MCOperandInfo OperandInfo363[] = { { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6765 static const MCOperandInfo OperandInfo364[] = { { AArch64::FPR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6766 static const MCOperandInfo OperandInfo365[] = { { AArch64::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6772 static const MCOperandInfo OperandInfo371[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6776 static const MCOperandInfo OperandInfo375[] = { { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6776 static const MCOperandInfo OperandInfo375[] = { { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6779 static const MCOperandInfo OperandInfo378[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6812 static const MCOperandInfo OperandInfo411[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6812 static const MCOperandInfo OperandInfo411[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6812 static const MCOperandInfo OperandInfo411[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6813 static const MCOperandInfo OperandInfo412[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6814 static const MCOperandInfo OperandInfo413[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6814 static const MCOperandInfo OperandInfo413[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6815 static const MCOperandInfo OperandInfo414[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6831 static const MCOperandInfo OperandInfo430[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
6842 static const MCOperandInfo OperandInfo441[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::PPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
6842 static const MCOperandInfo OperandInfo441[] = { { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::PPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
6843 static const MCOperandInfo OperandInfo442[] = { { AArch64::PPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6843 static const MCOperandInfo OperandInfo442[] = { { AArch64::PPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
gen/lib/Target/AArch64/AArch64GenRegisterBank.inc 94 (1u << (AArch64::GPR32RegClassID - 0)) |
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 3443 { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64::GPR32RegClassID, 1, true },
6812 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
6966 &AArch64MCRegisterClasses[GPR32RegClassID],
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 955 TRI->getRegClass(AArch64::GPR32RegClassID)->contains(StRt)) &&
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 67 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
242 case AArch64::GPR32RegClassID:
lib/Target/AArch64/AArch64RegisterInfo.cpp 545 case AArch64::GPR32RegClassID:
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 1117 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.RegNum);
1435 uint32_t Reg = RI->getRegClass(AArch64::GPR32RegClassID).getRegister(
1444 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(getReg()));
5604 AArch64MCRegisterClasses[AArch64::GPR32RegClassID];